Tamper Detection Memory Save with Delay

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Solution Overview

Problem

Existing methods for disabling a personal computer when unauthorized access occurs often result in data loss from volatile write caches and metadata damage, as they lack sufficient time for cache flush and metadata saving, and rely on costly battery or capacitor solutions.

Innovation Solution

A computer-implemented method and system that receives a tamper notification, starts a delay timer, initiates saving of volatile memory data to non-volatile storage, and powers down the device after a predetermined delay, ensuring data integrity without additional costly components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a tamper detection switch triggers immediate power FET shutdown, then system security is improved, but volatile write cache data is lost and metadata structures are damaged

Engineering Contradiction:
Improvesystem securityVSAvoidvolatile write cache data
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The system performs preliminary actions by initiating a cache flush sequence before the actual power shutdown. When tamper is detected, the system first activates the cache flush controller to transfer volatile cache data to non-volatile storage, then subsequently shuts down power. This preliminary data preservation action resolves the contradiction by ensuring data integrity while maintaining security shutdown capability.

Inventive Principle:
Principle #10Preliminary action

2Loss of information

If battery or power back-up capacitors are used to provide cache flush time, then data integrity is improved, but cost and component failure opportunities increase

Engineering Contradiction:
Improvecache data preservationVSAvoidpower back-up components
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The invention extracts the power backup components (batteries and capacitors) from the system entirely. Instead of using dedicated power preservation components, the system uses the existing power supply infrastructure combined with a controlled shutdown sequence. The cache flush controller manages data transfer using normal power rails, eliminating the need for separate backup power components while maintaining data integrity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system serves itself by using its existing power supply and control infrastructure to perform the cache flush operation. Rather than requiring external backup power sources, the system's own power controller and timing mechanisms coordinate the data preservation process, making the system self-sufficient and eliminating complex backup components.

Inventive Principle:
Principle #25Self-service

3Loss of information

If sufficient delay time is provided for cache flush, then data integrity is improved, but system response time to tamper is slowed

Engineering Contradiction:
Improvemetadata structure preservationVSAvoidtamper response time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The system implements dynamic timing control where the shutdown sequence is adaptively managed. The cache flush controller and power controller coordinate to perform data transfer operations during an extended but controlled time window, then rapidly complete the shutdown. This dynamic approach optimizes the balance between data preservation time and overall response time, allowing sufficient cache flush duration while maintaining fast tamper response.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20240211352A1Tamper detectection memory save with delay
Publication Date: 2024.06.27 LENOVO UNITED STATES INC
  • US20240211352A1 patent drawing
  • US20240211352A1 patent drawing
  • US20240211352A1 patent drawing

AI summary

A computer implemented method and system includes receiving a tamper notification responsive to improper opening of a device enclosure, starting a delay time timer in response to receiving the tamper signal, initiating saving of volatile memory data in a storage device to non-volatile storage, providing a power down notification signal to a device power controller in response to the timer reaching a predetermined state, and powering down the device in response to the power down notification signal.