Tandem Print Engine Color Registration Error Correction

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Solution Overview

Problem

Tandem print engines in printing systems face color registration errors due to mechanical and other variations, requiring adjustments in pixel clock frequencies, which increases complexity and cost with the use of multiple PLL circuits.

Innovation Solution

The method involves computing an adjusted resolution for color data to offset registration errors in print engines, allowing them to operate with a single pixel frequency, using calibration information and resolution data from a reference engine to adjust the color data for other engines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If pixel clock frequencies are adjusted for each color plane to correct registration errors, then color registration accuracy is improved, but device complexity increases due to requiring multiple PLL circuits

Engineering Contradiction:
Improvecolor registration accuracyVSAvoidnumber of PLL circuits
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the frequency adjustment functionality into a single reference PLL circuit that generates a base clock signal. All color planes share this single PLL, and registration corrections are achieved by adjusting pixel sampling positions in the digital domain rather than using separate PLL circuits for each color plane. This reduces the number of PLL circuits from multiple to one.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent replaces the hardware-based frequency adjustment mechanism (multiple PLL circuits) with a software/digital processing approach. Pixel registration corrections are implemented by adjusting pixel sampling positions through digital signal processing and coordinate transformation algorithms, substituting physical frequency tuning with computational methods.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If multiple PLL circuits are used to lock pixel clocks to different frequencies, then color registration is corrected, but manufacturing cost increases

Engineering Contradiction:
Improvecolor registration accuracyVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent consolidates the clock generation functionality into a single reference PLL circuit that serves all color planes. By sharing one PLL circuit instead of using separate PLLs for each color plane, the bill of materials is reduced, manufacturing complexity is lowered, and production costs are decreased while maintaining registration accuracy through digital processing.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single reference PLL circuit is designed to be universal, generating a base clock signal that is used by all color planes. The system achieves color-specific frequency adjustments through digital processing of the shared clock signal, making the PLL circuit multi-functional and reducing component costs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If separate pixel clocks are used for each print engine, then individual frequency adjustment is possible, but chip area is consumed by multiple PLL circuits

Engineering Contradiction:
Improvefrequency adjustment capabilityVSAvoidchip area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple clock generation functions into a single reference PLL circuit located on the host processor chip. This single circuit generates a master clock signal that is distributed to all color planes, eliminating the need for separate PLL circuits on each print engine or on the chip, thereby conserving valuable chip real estate.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a digital processing intermediary layer that receives the single reference clock signal and generates color-plane-specific timing through digital division and coordinate transformation. This intermediary digital processing layer enables frequency adjustment capabilities without requiring physical PLL circuits for each color plane, saving chip area.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8223390B2Systems and methods for reducing color registration errors in tandem engines
Publication Date: 2012.07.17 KONICA MINOLTA SYSTEMS LABORATORY INC
  • US8223390B2 patent drawing
  • US8223390B2 patent drawing
  • US8223390B2 patent drawing

AI summary

Systems and methods are provided for correcting color registration errors in a printing device comprising a plurality of print engines driven by a single pixel frequency clock. In some embodiments, the print engines can include a reference print engine and one or more non-reference print engines. An adjusted resolution may be computed for color data sent to each non-reference engine to offset color registration errors attributable to the non-reference engine. The adjusted resolution is computed using calibration information for the non-reference print engines relative to the reference engine, and resolution information for color data processed by the first reference engine. The resolution of color data processed by each non-reference print engine is adjusted according to the computed adjusted resolution for the non-reference engine and sent to the print engines for printing.