IC TAP Cell Placement Using Elongated Wells for Latch-Up Immunity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The placement of TAP cells in integrated circuit (IC) layouts for manufacturing ICs faces challenges such as process bottlenecks due to reduced lithography critical dimension and mixed channel effects, which affect latch-up immunity and area utilization.
Innovation Solution
The placement of first TAP cells of one semiconductor type in rows and columns, and second TAP cells of a different type in elongated configurations across multiple columns, allowing for improved latch-up immunity, reduced area occupation, and increased space for standard cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TAP cells are placed in traditional configurations to ensure latch-up immunity, then reliability is improved, but area occupation increases and process constraints are tightened
Solution Approach 1:
The patent segments TAP cells into different types (first TAP cells and second TAP cells) with different configurations. First TAP cells are placed in rows and columns, while second TAP cells are placed in elongated configurations across multiple columns. This segmentation allows optimization of latch-up immunity in different regions without uniformly increasing area occupation across the entire IC layout.
Solution Approach 2:
The patent applies different placement strategies to different types of TAP cells based on local requirements. First TAP cells use a standard row-column placement, while second TAP cells use elongated configurations that span multiple columns. This local quality approach ensures that each TAP cell type is optimally configured for its specific function and location, improving overall latch-up immunity without excessive area consumption.
2Reliability
If TAP cells are placed in traditional configurations to ensure latch-up immunity, then reliability is improved, but process constraints are tightened
Solution Approach 1:
By segmenting TAP cells into different types with different placement configurations, the patent reduces the uniformity requirements that constrain manufacturing processes. The varied placement patterns (standard vs. elongated) allow for more flexible process windows and reduce sensitivity to lithography variations, thereby easing process constraints while maintaining reliability.
Solution Approach 2:
The patent changes the placement parameters of TAP cells by introducing elongated configurations that span multiple columns, as opposed to traditional single-column placements. This parameter change in placement geometry reduces sensitivity to process variations and relaxes lithography critical dimension constraints, making manufacturing easier while preserving latch-up immunity.
3Area of stationary object
If TAP cells are placed in elongated configurations, then area usage is optimized, but device complexity increases
Solution Approach 1:
The patent segments the TAP cell population into two distinct types with different placement rules. First TAP cells follow traditional row-column placement, while second TAP cells use elongated configurations. This segmentation manages complexity by creating clear, distinct placement categories rather than requiring complex individual optimization for each TAP cell, thereby optimizing area usage without excessive complexity.
Solution Approach 2:
Instead of placing all TAP cells in the traditional uniform manner, the patent inverts the approach by introducing a second type of TAP cell with elongated configurations that span multiple columns. This inversion of the traditional placement paradigm enables better area utilization while maintaining manageable complexity through the clear distinction between the two TAP cell types.
Data Source
AI summary
A method of manufacturing an integrated circuit (IC) device includes forming, over a substrate, at least one first well region of a first semiconductor type, and a second well region of a second semiconductor type different from the first semiconductor type. The method further includes forming a plurality of first doped regions of the first semiconductor type over the at least one first well region, and a second doped region of the second semiconductor type over the second well region. Each of the plurality of first doped regions has a first length in a first direction. The second doped region extends in the first direction between at least two first doped regions among the plurality of first doped regions over a second length greater than the first length.