Merging TAP and WSP Architectures for Reduced Test Overhead
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Solution Overview
Problem
The implementation of both IEEE 1149.1 and IEEE P1500 test standards in integrated circuits (ICs) leads to increased circuit area overhead, test complexity, and limited access to IEEE P1500 for real-time operations due to separate test interfaces and architectures, resulting in wire routing and density issues.
Innovation Solution
The proposed solution involves partially or completely combining these test standards, allowing the TAP to control the P1500 architecture, and merging the TAP and WSP based architectures into a single optimized test interface to reduce the number of required test signals and enhance operational flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both IEEE 1149.1 and IEEE P1500 test standards are implemented separately, then both test standards can be used to test circuitry, but circuit area overhead and test complexity increase
Solution Approach 1:
The patent merges the TAP (IEEE 1149.1) and WSP (IEEE P1500) architectures into a unified test interface. The instruction register and data registers are shared between both standards, with the TAP state machine capable of controlling either the TAP path or the WSP path. This consolidation allows a single IC to support both IEEE 1149.1 and IEEE P1500 testing without requiring separate independent test interfaces, thereby reducing circuit area overhead and test complexity while maintaining versatility.
Solution Approach 2:
The unified test interface is designed to be universal, where the TAP state machine can function as either a TAP controller or a WSP controller depending on the operational mode. The same instruction register and data registers serve both IEEE 1149.1 and IEEE P1500 standards, allowing a single hardware structure to perform multiple testing functions according to different standards.
2Adaptability or versatility
If separate test interfaces are used for IEEE 1149.1 and IEEE P1500, then each standard can be fully supported, but wire routing and density issues arise
Solution Approach 1:
The patent combines the signal routing paths for both standards into a shared infrastructure. The TAP and WSP architectures share common instruction register and data register pathways, reducing the number of separate wires required. By merging the control logic and data paths, the solution minimizes wire routing area and improves layout density while maintaining full support for both IEEE 1149.1 and IEEE P1500 standards.
3Adaptability or versatility
If IEEE P1500 is implemented with separate architecture, then P1500 operations can be performed, but real-time access is limited
Solution Approach 1:
The patent merges the WSP (IEEE P1500) architecture into the TAP (IEEE 1149.1) framework, allowing the TAP state machine to control the WSP path for real-time operations. This integration enables the P1500 functionality to be accessed through the existing TAP interface, which is already optimized for real-time control and monitoring, thereby improving ease of operation while maintaining P1500 capability.
Data Source
AI summary
In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.