Tape Wiring Substrate Dispersion Patterns for EMI Noise
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Solution Overview
Problem
Conventional tape packaging technologies face issues with EMI noise characteristics due to thermal stress-induced deformation of tape wiring substrates, leading to poor bonding between input/output wiring patterns and electrode bumps, especially with finer pitches and wider non-wiring regions.
Innovation Solution
Incorporating dispersion wiring patterns and connecting wiring patterns on the tape wiring substrate to compensate for irregularities and thermal stresses, ensuring regular pitch and improved bonding between input/output wiring patterns and electrode bumps, thereby enhancing EMI noise characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the pitch of wiring patterns is reduced to enable smaller flat display devices, then the device size decreases, but the EMI noise characteristics deteriorate due to thermal stress-induced deformation
Solution Approach 1:
The tape wiring substrate is divided into wiring regions and non-wiring regions. The non-wiring regions act as separate segments that absorb thermal stress deformation, preventing it from affecting the wiring patterns. This segmentation allows fine pitch wiring to be maintained without EMI noise degradation.
Solution Approach 2:
Non-wiring regions serve as intermediary zones between different wiring patterns and between the chip mounting area and the substrate edges. These intermediary regions absorb thermal stress and prevent direct transmission of deformation to the critical wiring patterns, thereby protecting EMI noise characteristics.
2Adaptability or versatility
If wider non-wiring regions are used to accommodate chip mounting, then chip placement flexibility increases, but bonding between input/output wiring patterns and electrode bumps deteriorates due to thermal stress deformation
Solution Approach 1:
The substrate is segmented into distinct wiring regions and non-wiring regions. The non-wiring regions are positioned to absorb thermal stress away from the bonding areas, ensuring that chip placement flexibility is maintained while bonding reliability is protected from deformation effects.
Solution Approach 2:
Different regions of the substrate are given different functional qualities: wiring regions are optimized for electrical connectivity with precise patterns, while non-wiring regions are optimized for absorbing thermal stress. This local differentiation allows wide non-wiring regions to coexist with reliable bonding in the wiring regions.
3Productivity
If finer pitch wiring patterns are implemented, then device integration increases, but manufacturing precision requirements increase due to thermal stress-induced deformation
Solution Approach 1:
By segmenting the substrate into wiring and non-wiring regions, the patent isolates the fine pitch wiring patterns from thermal stress deformation. This allows high device integration through fine pitch wiring without requiring excessive manufacturing precision, as the non-wiring regions absorb the deformation.
Solution Approach 2:
Non-wiring regions are strategically placed beforehand to cushion against thermal stress deformation before it can affect the wiring patterns. This preemptive cushioning protects the precision of fine pitch wiring during thermal cycling, reducing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the likelihood of faults associated with EMI noise characteristics by ensuring stable bonding and dispersion of thermal stresses, improving the overall performance of tape packaging.
Implementation Method 1
thermal stress-induced deformation of tape wiring substrates
Data Source
AI summary
A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.


