Tape Wiring Substrate Dummy Region Routing

Solution Overview

Problem

The existing semiconductor package designs face challenges in minimizing the width of the tape wiring substrate when a semiconductor chip with an increased width due to added dummy chip regions is used, as they require a corresponding increase in the substrate width, which can lead to larger and more costly packages.

Innovation Solution

The design incorporates a tape wiring substrate with a base film and wiring patterns where the first wiring patterns extend on a dummy mounting region, allowing the substrate to maintain a reduced width by utilizing the dummy chip regions as paths for the wiring patterns, thereby avoiding the need for increased substrate width.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the substrate width is increased to accommodate the wider semiconductor chip with dummy chip regions, then the chip can be properly mounted with extended wiring patterns, but the package size increases and manufacturing cost increases

Engineering Contradiction:

Improvechip width accommodationVSAvoidsubstrate width

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent applies dimensionality change by routing wiring patterns from the two-dimensional chip surface into the third dimension using vias and conductive plugs. Wiring patterns extend through the substrate thickness rather than only across its width, allowing the chip to be mounted on a narrower substrate while maintaining electrical connectivity to dummy chip regions.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent utilizes a perforated substrate structure with through-holes that are filled with conductive material. This porous-like structure allows wiring patterns to pass through the substrate vertically, enabling electrical connection to the dummy chip regions without increasing the substrate's horizontal width.

Inventive Principle:

Principle #31Porous materials

2Adaptability or versatility

If the substrate width is increased to accommodate the wider semiconductor chip with dummy chip regions, then the chip can be properly mounted with extended wiring patterns, but the manufacturing cost increases

Engineering Contradiction:

Improvechip width accommodationVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent applies dimensionality change by routing wiring patterns from the two-dimensional chip surface into the third dimension using vias and conductive plugs. Wiring patterns extend through the substrate thickness rather than only across its width, allowing the chip to be mounted on a narrower substrate while maintaining electrical connectivity to dummy chip regions.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent utilizes a perforated substrate structure with through-holes that are filled with conductive material. This porous-like structure allows wiring patterns to pass through the substrate vertically, enabling electrical connection to the dummy chip regions without increasing the substrate's horizontal width.

Inventive Principle:

Principle #31Porous materials

Data Source

PatentUS9922921B2Tape wiring substrate, semiconductor package, and display apparatus including semiconductor package

Publication Date: 2018.03.20 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes: a semiconductor chip including an effective chip region at a center of the semiconductor chip and in which pads connected to chip wirings are formed, and a dummy chip region at a side of the effective chip region and in which pads not connected to the chip wirings are formed; a base film including a chip mounting section on which the semiconductor chip is mounted; and a plurality of wiring patterns disposed on the base film and electrically connected to the chip wirings of the semiconductor chip, wherein first wiring patterns, which are a part of the plurality of wiring patterns, extend on a first region of the chip mounting section corresponding to the dummy chip region.