Taper Etching for Inclined Active Island Corners in Semiconductor Devices

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge in semiconductor manufacturing lies in forming reliable semiconductor devices at increasingly smaller sizes, where the complexity of fabrication processes increases due to decreasing feature sizes, leading to difficulties in forming gate insulating layers with appropriate stress conditions on active islands.

Innovation Solution

A method involving a taper etching process to form inclined surfaces on the substrate, followed by the deposition of insulating layers and gate insulating layers, which reduces stress at the top corners of active islands, enabling improved formation and continuity of gate insulating layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity increases and reliability deteriorates

Engineering Contradiction:
Improveproduction efficiencyVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by creating inclined surfaces at specific locations (top corners of active islands) rather than modifying the entire substrate. This localized geometric modification reduces stress concentration at critical points where gate insulating layers are most vulnerable, thereby improving reliability without requiring changes to the overall fabrication process or feature sizes

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If feature sizes are decreased to increase functional density, then chip area is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improvechip areaVSAvoidfabrication precision
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming inclined surfaces on active islands before depositing gate insulating layers. This pre-modification of the substrate geometry prepares the surface to reduce stress concentration during subsequent processing steps, enabling better control of gate insulating layer formation and reducing the precision requirements for later fabrication steps

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If conventional fabrication processes are used on flat substrates, then process simplicity is maintained, but gate insulating layer continuity and reliability deteriorate due to stress concentration

Engineering Contradiction:
Improveprocess complexityVSAvoidgate insulating layer reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies curvature by replacing flat surfaces with inclined surfaces at the top corners of active islands. This geometric curvature redistributes stress more evenly during gate insulating layer deposition, preventing stress concentration that would otherwise cause cracking or discontinuities, thereby improving layer continuity and reliability with minimal added process complexity

Inventive Principle:
Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability of gate insulating layers and improves the yield of transistor devices by reducing stress at the top corners of active islands, ensuring effective electrical insulation and continuous coverage.

Implementation Method 1

performing a first plasma etching process on a substrate to form a first trench in the substrate

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 2

after the formation of the isolation structure, performing an oxidation process on the substrate to form a continuous gate insulating layer on the top surface and the first inclined surface

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS10141401B2Method for forming semiconductor device structure
Publication Date: 2018.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10141401B2 patent drawing
  • US10141401B2 patent drawing
  • US10141401B2 patent drawing

AI summary

A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.