Tapered Anti-Fuse on Semiconductor Fin for Low-Voltage OTP
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Solution Overview
Problem
Existing One-Time-Programmable (OTP) memory devices require high voltages or currents for programming, making them incompatible with current copper damascene processes and increasing complexity and cost in fabricating integrated circuits.
Innovation Solution
The development of OTP anti-fuses formed on semiconductor fins using selective epitaxial growth to create epitaxy regions with facets, which are programmed by applying a voltage to break down dielectric material and lower resistance, allowing for efficient programming and reading without the need for high voltages or currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing OTP memory devices use metal fuses or gate oxide fuses, then programming capability is achieved, but high voltages or high currents are required which increases design complexity and fabrication cost
Solution Approach 1:
The patent changes the electrical parameters of the anti-fuse structure by forming tapered conductive regions with varying cross-sectional areas, allowing programming at lower voltages and currents compared to conventional OTP devices. The tapered geometry creates a controlled electric field distribution that enables breakdown at reduced stress conditions.
Solution Approach 2:
The patent introduces a vertical dimension to the conductive regions by forming tapered structures with different cross-sectional areas at different heights. This dimensional change allows the electric field to be distributed through the volume of the structure rather than concentrated at a single plane, reducing the peak voltage and current requirements for programming.
2Ease of manufacture
If existing OTP memory devices use aluminum interconnect technologies, then fabrication is achieved, but compatibility with current copper damascene processes is lost
Solution Approach 1:
The patent creates an anti-fuse structure that can be integrated into both copper damascene and aluminum interconnect processes. The tapered conductive regions can be formed using standard deposition and etching techniques that are compatible with modern CMOS fabrication, making the structure universally applicable across different process technologies.
Solution Approach 2:
The patent segments the conductive path into multiple regions with varying cross-sectional areas, creating a tapered structure. This segmentation allows each region to be formed using standard fabrication steps, enabling integration with existing copper damascene or aluminum processes without requiring a complete process overhaul.
3Device complexity
If anti-fuses are formed with standard processes, then fabrication complexity is reduced, but programming efficiency and success rate may be compromised
Solution Approach 1:
The patent performs preliminary structuring by forming tapered conductive regions with optimized geometry before the programming step. This preliminary action ensures that when programming is applied, the electric field is already optimally distributed, leading to higher programming success rates and efficiency without adding complex fabrication steps.
Solution Approach 2:
The patent optimizes the geometric parameters of the conductive regions, specifically creating tapered structures with controlled aspect ratios and cross-sectional variations. These parameter changes enhance the programming efficiency by creating favorable electric field conditions while maintaining compatibility with standard fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density OTP anti-fuses that can be programmed using standard front-end processes without additional masks or steps, increasing successful programming rates and efficiency while reducing fabrication complexity and cost.
Implementation Method 1
selective epitaxial growth to create epitaxy regions with facets
Implementation Method 2
programmed by applying a voltage to break down dielectric material and lower resistance
Data Source
AI summary
A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.