Tapered Bit Line Structure for Reliable Landing Pad Etching
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Solution Overview
Problem
The semiconductor industry faces challenges in precise control of lithography as it advances to smaller technology nodes, leading to issues such as disconnected landing pads due to sharp corners of bit line structures during etching operations, affecting device performance and yield.
Innovation Solution
A semiconductor structure and manufacturing method involving a bit line structure with a tapered configuration, including a cylindrical portion and a step portion, surrounded by a polysilicon layer and spacers, which are formed through multiple etching operations to prevent sharp corners and ensure precise dimensions, allowing for better control and reduced risk of electrical disconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography patterning is used to form bit line structures, then manufacturing process simplicity is maintained, but manufacturing precision deteriorates due to inability to control sharp corners and tapered profiles at advanced technology nodes
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure with the desired tapered profile and step portions before forming the bit line structure. The mandrel is created through conformal deposition of spacer materials around a sacrificial core, establishing the final bit line geometry in advance. This preliminary structuring enables precise profile control that would be difficult to achieve through direct lithography patterning at advanced technology nodes.
Solution Approach 2:
The patent uses a mandrel structure as an intermediary element to transfer the desired bit line profile from a sacrificial core to the final conductive structure. The mandrel acts as a temporary mediator that defines the tapered and stepped geometry, which is then replicated in the bit line material through conformal deposition and selective removal of the sacrificial core. This intermediary approach enables precise profile control without requiring direct lithographic patterning of the final structure.
2Reliability
If sharp corners are present in bit line structures, then manufacturing simplicity is maintained, but reliability deteriorates due to disconnected landing pads during etching operations
Solution Approach 1:
The patent applies spheroidality by replacing sharp corners with curved, tapered profiles in the bit line structure. The mandrel-based fabrication process naturally produces smooth transitions and rounded corners through conformal spacer deposition, eliminating the sharp geometric features that cause etching discontinuities. This curvature in the bit line profile ensures continuous electrical connection to landing pads while maintaining manufacturing feasibility through the intermediary mandrel approach.
3Manufacturing precision
If conventional single-step etching is used, then process time is reduced, but manufacturing precision deteriorates due to inability to achieve selective height reduction of polysilicon layer
Solution Approach 1:
The patent applies segmentation by dividing the polysilicon layer height reduction into multiple selective etching steps. Different portions of the polysilicon layer are removed at different stages using etching processes with varying selectivity and depth control. This segmented approach allows precise height differentiation between various bit line regions and the polysilicon layer, achieving the required dimensional precision that would be impossible in a single etching step, while the use of mandrel-based patterning maintains reasonable throughput.
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.