Tapered Bottom Electrode for PCRAM Field Confinement
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Solution Overview
Problem
Existing phase change random access memory (PCRAM) and resistive random access memory (RRAM) technologies face limitations in reducing operating current and voltage as device scaling-down continues, despite their fast read/write times and high scalability.
Innovation Solution
The solution involves disposing bottom electrodes on the sidewalls of dielectric patterns in PCRAM or RRAM, which reduces the contact area with storage patterns, thereby efficiently confining the heat or electrical field, leading to lower operating currents and voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device scaling-down continues in existing PCRAM or RRAM, then device density increases, but operating current and voltage cannot be reduced sufficiently
Solution Approach 1:
The bottom electrode is designed with non-uniform cross-sectional area along its length, creating local quality variations. The cross-sectional area is smaller at the interface with the storage pattern and larger at the heater interface, concentrating the heat or electrical field where needed while reducing overall current requirements
Solution Approach 2:
The invention transitions from a conventional planar electrode structure to a three-dimensional tapered structure. By extending the electrode in the vertical dimension with varying cross-section, it achieves better field confinement and reduced current requirements compared to flat two-dimensional electrodes
2Quantity of substance
If device scaling-down continues in existing PCRAM or RRAM, then device density increases, but operating voltage cannot be reduced sufficiently
Solution Approach 1:
The tapered geometry creates local quality variations in the electrical field distribution, concentrating the field at the narrow interface region with the storage pattern. This localized field concentration achieves effective switching at lower voltages while maintaining high device density
Solution Approach 2:
By introducing vertical dimensionality with tapered sides, the electrode achieves three-dimensional field confinement that reduces the voltage required for operation, enabling high-density scaling without proportionally increasing operating voltage
3Loss of energy
If contact area between electrode and storage pattern is reduced, then heat or electrical field confinement improves, but manufacturing precision requirements increase
Solution Approach 1:
The invention changes the geometric parameters of the electrode from uniform to tapered, with specific emphasis on the cross-sectional area variation. This parameter change achieves better field confinement while the gradual taper provides manufacturing tolerance that reduces precision requirements compared to abrupt geometry changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the operating current and voltage of PCRAM or RRAM, enhancing their performance and efficiency by minimizing the contact area between electrodes and storage patterns.
Implementation Method 1
the contact area between the top ends of the bottom electrodes and the storage patterns is small enough to efficiently confine the heat field or electrical field in PCRAM or RRAM
Implementation Method 2
the contact area between the top ends of the bottom electrodes and the storage patterns is small enough to efficiently confine the heat field or electrical field in PCRAM or RRAM
Implementation Method 3
the material may be heated, for example, by passing current through a heating element to enters its crystalline state
Data Source
AI summary
Provided are a memory cell and a method of forming the same. The memory cell includes a first dielectric pattern, a second dielectric pattern, a first bottom electrode, a first storage pattern, and a first top electrode. The first bottom electrode is disposed between the first dielectric pattern and the second dielectric pattern, and the first bottom electrode interfaces a first sidewall of the first dielectric pattern and a sidewall of the second dielectric pattern. The first storage pattern is disposed on the first dielectric pattern, the second dielectric pattern and the first bottom electrode, wherein the first storage pattern is electrically connected to the first bottom electrode. The first storage pattern is between the first bottom electrode and the first top electrode. A semiconductor die including a memory array is also provided.