Tapered Chip Bonding Pad Geometry for Reliable Package Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages face challenges in achieving reliable bonding between chip connection terminals and chip bonding pads due to inadequate alignment and contact area, leading to poor structural and electrical connectivity, especially with tapered chip bonding pads having specific dimensions.
Innovation Solution
A package substrate with a chip bonding pad featuring a tapered shape, where the horizontal cross-sectional area decreases vertically, providing a trapezoidal cross-section with a top side length of 5 μm to 25 μm and a bottom side length 1.1 to 6 times that of the top side, enhancing contact area and alignment between the chip connection terminal and the chip bonding pad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a chip bonding pad with a tapered shape is used, then bonding reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The chip bonding pad is designed with a tapered shape in advance, where the upper surface area is larger than the lower surface area. This preliminary geometric configuration ensures that when the chip connection terminal is mounted, it naturally aligns with the larger upper surface area, providing a tolerance buffer that improves bonding reliability while accommodating variations in mounting precision.
Solution Approach 2:
The chip bonding pad employs specific dimensional parameters: the upper surface area is designed to be larger than the lower surface area, with the horizontal length of the upper surface being about 20 μm to 30 μm. By optimizing these geometric parameters, the design achieves improved bonding reliability while maintaining manufacturability within standard precision capabilities.
2Area of stationary object
If the horizontal length of the chip bonding pad is increased, then contact area is improved, but device complexity increases
Solution Approach 1:
Instead of uniformly increasing the chip bonding pad dimensions in all directions, the design applies dimensional differentiation vertically: the upper surface area is made larger than the lower surface area through the tapered configuration. This dimensional approach increases the effective contact area for bonding while maintaining a compact overall footprint, thereby avoiding increased device complexity.
Solution Approach 2:
The chip bonding pad features non-uniform local geometry where the upper surface area is specifically enlarged compared to the lower surface area. This local quality enhancement concentrates the area increase at the bonding interface where it is most needed, rather than uniformly expanding the entire pad structure, thus improving contact area without proportionally increasing device complexity.
Data Source
AI summary
A package substrate includes an insulating layer having a mounting surface; a wiring pattern extending in the insulating layer; and a chip bonding pad provided on the mounting surface of the insulating layer and connected to the wiring pattern, the chip bonding pad having a tapered shape in which a horizontal cross-sectional area thereof gradually decreases away from the mounting surface of the insulating layer in a vertical direction. A portion of the chip bonding pad closest to the mounting surface of the insulating layer has a horizontal length of about 20 micrometers (μm) to about 30 μm.