Tapered Conductive Features for Via Alignment
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Solution Overview
Problem
The semiconductor industry faces challenges in forming conductive features to connect devices in ICs due to misalignment issues, particularly as ICs miniaturize, leading to defects and reliability problems from via-wire misalignment and excessive etching in multilayer interconnects.
Innovation Solution
A method for fabricating conductive features with a tapered profile, using a patterned mask layer, etch stop, and anti-reflective coating, followed by selective etching and chemical mechanical polishing, to prevent via misalignment, where the conductive feature is wider at the bottom and narrower at the top, allowing for more flexibility in via formation and reducing damage to low-k dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching methods are used to form conductive features, then the fabrication process is simple, but via misalignment occurs and excessive etching damages low-k dielectric materials
Solution Approach 1:
The method performs preliminary actions by forming a tapered profile on the conductive feature before via formation. The tapered sides are created through selective etching of the conductive layer at different rates or angles, preparing the structure in advance to guide subsequent via etching and prevent misalignment.
Solution Approach 2:
The invention changes the geometric parameters of the conductive feature by creating a tapered profile with different widths at the top and bottom. This parameter modification allows the via to be formed more easily within the conductive feature, providing alignment tolerance and preventing misalignment issues.
2Adaptability or versatility
If the conductive feature has a uniform width profile, then fabrication is easier, but via formation flexibility is reduced and misalignment occurs
Solution Approach 1:
The invention applies asymmetry by creating a conductive feature with a tapered profile where the width varies along the vertical axis. The feature has a first width at the top and a second width at the bottom, with the widths being different. This asymmetric geometry provides flexibility for via formation while maintaining manufacturing precision through controlled etching processes.
3Productivity
If standard etching is used without tapered profiling, then the process is faster, but damage to low-k dielectric materials occurs
Solution Approach 1:
The method applies local quality by creating different etching characteristics at different locations of the conductive feature. The tapered profile is formed by selectively etching the conductive layer with different depths or rates at the top versus the bottom, allowing localized control of the etching process to protect the underlying low-k dielectric material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents via misalignment and reduces damage to low-k dielectric materials, enhancing the reliability and performance of ICs by providing additional space for via formation and maintaining the integrity of insulating materials.
Implementation Method 1
chemical mechanical polishing
Data Source
AI summary
A method includes forming a patterned mask layer over a conductive layer; forming a first dielectric layer over the patterned mask layer and the conductive layer; selectively etching the first dielectric layer, thereby exposing an upper surface of the patterned mask layer, wherein the upper surface of the first dielectric layer is lower than a top surface of the patterned mask layer; removing the patterned mask layer; and selectively etching the conductive layer to form a conductive feature having a tapered profile.