Tapered Conductive Segments in Embedded Semiconductor Substrates
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Solution Overview
Problem
The manufacturing of semiconductor packages with increased I/O connections faces challenges due to increased sizes and costs, as well as difficulties in controlling the line width/line space of circuit layers, leading to low yield and high costs due to warpage issues from thermal expansion mismatches and the need for wet processes.
Innovation Solution
A stacked structure with a gradually increasing reflective index is used, allowing precise exposure and development of photoresist layers without materials with different coefficients of thermal expansion, eliminating the need for wet processes and improving yield by reducing exposure areas and controlling circuit layer sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If bonding pad density is increased to minimize package size, then package size is reduced, but line width/line space of circuit layer decreases making manufacturing difficult
Solution Approach 1:
The patent introduces a tapered dimension to the conductive segments, where the width varies from a first width at the first surface to a second width at the second surface. This dimensional change allows the circuit layer to maintain adequate line width for manufacturability at the bonding pad level while achieving compact routing in the deeper layers, thus reducing overall package size without sacrificing manufacturing precision
Solution Approach 2:
The patent embeds multiple circuit layers within the dielectric structure, with conductive segments nested at different depths. The first circuit layer is embedded in the first dielectric structure, and second circuit layers can be embedded in second dielectric structures. This nesting allows efficient use of vertical space to reduce package footprint while maintaining adequate line dimensions for manufacturing
2Reliability
If semiconductor chips are integrated with more electronic components to achieve better electrical performance, then electrical performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the geometric parameters of conductive segments by implementing tapered widths at different depths. This allows optimization of electrical performance through controlled impedance and signal integrity while using cost-effective manufacturing processes that don't require extremely fine line dimensions, thus improving electrical performance without proportionally increasing manufacturing cost
3Quantity of substance
If line width/line space is decreased to increase bonding pad density, then bonding pad density increases, but manufacturing yield decreases due to warpage issues
Solution Approach 1:
By implementing tapered conductive segments with different widths at different depths, the patent allows adequate material volume and structural support at the surface level to minimize warpage, while achieving high bonding pad density through efficient vertical routing in deeper layers. This maintains manufacturing yield while increasing bonding pad density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of circuit layer sizes, reduces costs by eliminating wet processes, and enhances the yield of fine-line circuit layers, allowing for smaller line widths and spaces, thus addressing the challenges of increased I/O connections and size issues in semiconductor packages.
Implementation Method 1
a reflective index of the stacked structure increases gradually from the first outermost layer though the at least one intermediate layer to the second outermost layer
Implementation Method 2
emitting a light beam near the first outermost layer to pass through the first outermost layer and the intermediate layer to irradiate the second outermost layer
Implementation Method 3
sputtering a metal structure in the openings of the second outermost layer to form a first circuit layer
Data Source
AI summary
A semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. A width of the first portion of the conductive segment is different from a width of the second portion of the conductive segment.