Tapered Contact Holes in Thin Film Transistor Array Panels
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Solution Overview
Problem
In liquid crystal displays, the formation of field generating electrodes over thin film transistor array panels often results in insulating layers that can lead to widened contact holes, increasing the risk of short circuits and resistance issues due to the lack of precise alignment and structure in the contact holes.
Innovation Solution
A self-aligned tapered structure is achieved in the contact holes of the thin film transistor array panel by etching an organic layer using a photosensitive film pattern, ensuring that the contact holes coincide with or are smaller than the openings of the field generating electrodes, thereby preventing short circuits and maintaining reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form contact holes through insulating layers, then the contact holes can be formed to connect the thin film transistor and field generating electrode, but the contact holes tend to widen due to lack of precise alignment, increasing the risk of short circuits
Solution Approach 1:
The photosensitive film pattern is formed in advance with a design that anticipates the tapered etching process. The pattern includes an upper opening larger than the lower contact hole, which pre-compensates for the expected etching widening. This preliminary design ensures that even after etching-induced widening, the contact hole remains properly aligned and contained within the field generating electrode opening, preventing short circuits.
Solution Approach 2:
The invention creates a cushioning effect by designing the photosensitive film pattern with a larger upper opening that provides a buffer zone. This cushioning structure accommodates the inevitable etching widening while maintaining proper alignment. The extra material in the upper portion of the photosensitive film acts as a protective cushion that prevents the etched contact hole from exceeding the boundaries of the field generating electrode opening.
2Reliability
If the contact holes are made larger to ensure proper connection, then electrical connection is improved, but the risk of short circuits increases due to widened contact holes
Solution Approach 1:
The contact hole structure exhibits local quality variation through its tapered geometry. The upper portion has a larger diameter to ensure adequate electrical connection and alignment tolerance, while the lower portion maintains a smaller, more precise diameter that fits within the field generating electrode opening. This local differentiation of hole diameter allows the contact hole to simultaneously achieve good electrical connection while preventing short circuits.
3Reliability
If multiple insulating layers are used between the thin film transistor and field generating electrode, then insulation performance is improved, but the complexity of alignment increases making precise contact hole formation difficult
Solution Approach 1:
The photosensitive film pattern serves multiple functions simultaneously: it acts as an etch mask for forming contact holes through multiple insulating layers, defines the alignment reference for the field generating electrode, and provides the tapered geometry that compensates for etching effects. This multi-functional design simplifies the overall process by using a single patterned layer to accomplish what would otherwise require multiple separate alignment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-aligned tapered structure effectively prevents contact hole widening and short circuits, enhancing the reliability and performance of the thin film transistor array panel by ensuring precise alignment and reduced electrical resistance.
Implementation Method 1
etching an organic layer using a photosensitive film pattern
Data Source
AI summary
A thin film transistor array panel includes a substrate; a gate line located over the substrate and including a gate pad portion; a data line located over the gate line and including a source electrode and a data pad portion; a drain electrode; a first passivation layer located over the data line and the drain electrode; an organic insulating layer located over the first passivation layer and having a contact hole; a first field generating electrode located over the organic insulating layer and having an opening; a second passivation layer located over the first field generating electrode; and a second field generating electrode located over the second passivation layer. The contact hole coincides with or is smaller than the opening, and the contact hole has a tapered structure.


