Tapered Contact Plug for 3D Stacked Semiconductor Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving a small area footprint, high integration, high speed operation, low power consumption, high productivity, and high manufacturing yield, particularly in the use of oxide semiconductors for transistors.
Innovation Solution
A semiconductor device design incorporating a transistor with an oxide semiconductor and a silicon transistor, featuring a contact plug structure that penetrates multiple insulating layers, allowing for electrical connection between the transistors and reducing the area occupied by the circuit while maintaining high integration and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional transistor structure is used, then the device can be manufactured with standard processes, but the area occupied by the circuit is large and integration is limited
Solution Approach 1:
The patent implements a three-dimensional stacked transistor structure where an oxide semiconductor transistor is formed above a silicon substrate transistor. This vertical stacking approach transitions from planar two-dimensional layout to three-dimensional configuration, enabling multiple transistors to occupy the same footprint area and significantly reducing the overall circuit area while maintaining manufacturability through established semiconductor fabrication processes
2Use of energy by moving object
If oxide semiconductor transistors are used, then power consumption is reduced due to low leakage current, but manufacturing precision and integration with silicon-based devices are challenging
Solution Approach 1:
The patent merges oxide semiconductor transistor technology with conventional silicon-based transistor manufacturing by forming the oxide semiconductor transistor above the silicon substrate in an integrated structure. This combination allows the device to leverage the low leakage current properties of oxide semiconductors for reduced power consumption while utilizing established silicon fabrication processes to maintain manufacturing precision and enable seamless integration with existing CMOS technology
Solution Approach 2:
The patent employs a tapered contact plug structure where the diameter changes in the depth direction, being smaller at the interface between the second insulating layer and the conductive layer. This curved/tapered geometry improves manufacturing precision by facilitating proper alignment and electrical connection between the oxide semiconductor transistor and underlying structures, thereby enhancing integration precision while maintaining the power consumption benefits of oxide semiconductor material
3Area of stationary object
If high integration is achieved through stacking, then area is reduced, but manufacturing complexity and yield may decrease
Solution Approach 1:
The patent segments the transistor structure into distinct functional layers including a silicon substrate transistor, insulating layers, and an oxide semiconductor transistor formed above. This segmentation into manageable layers with clear interfaces allows each layer to be manufactured and characterized independently using standard semiconductor processes, reducing overall manufacturing complexity despite the three-dimensional integrated structure and improving production yield
Data Source
AI summary
A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer. The conductive layer is between the first insulating layer and the second insulating layer. The first insulating layer, the conductive layer, and the second insulating layer overlap with each other in a region. A contact plug penetrates the first insulating layer, the conductive layer, and the second insulating layer. In a depth direction from the second insulating layer to the first insulating layer, a diameter of the contact plug changes to a smaller value at an interface between the second insulating layer and the conductive layer.