Tapered Alignable Contacts for Sub-Micron Chip Registration
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Solution Overview
Problem
Existing methods for 3D integration of integrated circuits lack the requisite alignment accuracy to match the fine pitch dimensions of current IC technologies, leading to significant deficiencies in electrical integrity and throughput, and do not allow for correction of initial misalignments or re-work of parts.
Innovation Solution
The use of tapered alignable-contact microstructures, fabricated using standard IC processes, which correct initial lateral and rotational misalignments by transferring z-directed force into in-plane forces during the bonding process, allowing for sub-100 nm registration and temporary assembly for verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional 3D integration methods (TSV, wire bonding, interposers) are used, then integration is achievable, but alignment accuracy is insufficient for fine pitch dimensions
Solution Approach 1:
The patent applies preliminary action by pre-forming tapered mechanical alignment aids directly into the bond pads during standard IC fabrication processes before stacking. These alignment aids are created in advance with precise tapered geometries that will later guide and correct alignment during the bonding operation, eliminating the need for complex post-fabrication alignment systems.
Solution Approach 2:
The patent introduces tapered mechanical alignment aids as intermediary structures between the bond pad and the opposing component. These alignment aids act as mediators that translate and correct misalignments by converting z-directed bonding forces into in-plane corrective forces, enabling accurate alignment without requiring complex external alignment equipment.
2Manufacturing precision
If high precision alignment equipment is used to achieve sub-micron registration, then alignment accuracy improves, but throughput decreases and cost increases
Solution Approach 1:
The patent implements self-service by designing alignment aids that automatically correct their own alignment errors during the bonding process. The tapered geometry enables the alignment aids to self-adjust and correct misalignments through force redistribution, eliminating the need for complex external alignment systems and enabling use of less precise, higher-throughput placement equipment.
3Productivity
If permanent bonding is performed without verification, then throughput is high, but misaligned components cannot be re-worked
Solution Approach 1:
The patent applies beforehand cushioning by creating compliant, tapered alignment aids that can accommodate and correct misalignments during bonding. This design provides a buffer that allows for verification and potential re-work, as the tapered structures can be separated and re-positioned without damage, unlike rigid permanent bonding structures.
4Manufacturing precision
If alignment aids consume significant IC real estate, then alignment capability improves, but device area increases
Solution Approach 1:
The patent merges the alignment function with the electrical bonding function by integrating tapered mechanical alignment aids directly into the bond pad structures. This combination eliminates the need for separate alignment features, as the same structures that make electrical contact also provide alignment correction, thereby consuming minimal IC real estate while delivering superior alignment capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Provides a 10× improvement in registration accuracy, enabling dense integration of face-to-face semiconductor ICs with 1 μm line/space, correcting ±1 μm misalignments, and allowing for temporary assembly and re-work of components.
Implementation Method 1
The tapered alignable-contact microstructures are designed to force shifts in the x and y directions (lateral, in-plane) by transferring the z-directed force (between the components) that occurs during the approach of the pair into an in-plane force that shifts the components positions into accurate registration.
Data Source
AI summary
A method and apparatus for laterally urging two semiconductor chips, dies or wafers into an improved state of registration with each other, the method and apparatus employing microstructures comprising: a first microstructure disposed on a first major surface of a first one of said two semiconductor chips, dies or wafers, wherein the first microstructure includes a sidewall which is tapered thereby disposing it at an acute angle compared to a perpendicular of said first major surface, and a second microstructure disposed on a first surface of a second one of said two semiconductor chips, dies or wafers, wherein the shape of the second microstructure is complementary to, and mates with or contacts, in use, the first microstructure, the second microstructure including a surface which contacts said sidewall when the first and second microstructures are mated or being mated, the sidewall of the first microstructure and the surface of the second microstructure imparting a lateral force for urging the two semiconductor chips, dies or wafers into said improved state of registration.