Tapered Data Storage Patterns for 3D Memory Reliability
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Solution Overview
Problem
Next-generation memory devices with 3D structures face reliability issues due to unexpected defects, which affect integration density and performance.
Innovation Solution
A semiconductor device design featuring conductive lines, data storage structures with specific electrode and pattern configurations, and an etch stop layer, along with a manufacturing method that includes forming conductive lines, data storage electrodes, and tapered data storage patterns to enhance reliability and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are arranged in a three-dimensional (3D) structure to increase integration density, then integration density is improved, but unexpected defects occur and reliability is reduced
Solution Approach 1:
The patent transitions from planar (2D) memory cell arrangement to three-dimensional (3D) stacking architecture. Multiple memory cell layers are stacked vertically along the thickness direction, with each layer containing bit lines, word lines, and memory elements arranged in specific three-dimensional configurations. This dimensional transition enables significantly higher integration density while maintaining reliability through careful structural design including etch stop layers and precise dimensional control of conductive patterns.
2Reliability
If data storage patterns are formed with specific width variations to improve reliability, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent employs asymmetric width variations in data storage patterns where the pattern width changes along its length. Specifically, first portions of data storage patterns have different widths than second portions, creating tapered or stepped configurations. This asymmetric design improves reliability by optimizing current distribution and reducing defects at pattern edges, while the complexity is managed through systematic formation processes using sequential etching and deposition steps.
Solution Approach 2:
Different portions of the data storage pattern are given different local properties through width variations. The first portions and second portions have distinct widths tailored to their specific functional requirements within the memory cell structure. This local quality variation optimizes performance at different locations while maintaining overall pattern integrity and reducing manufacturing defects.
3Reliability
If etch stop layers are added adjacent to data storage patterns to reduce defects, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
Etch stop layers are formed in advance before the data storage patterns are created. These preliminary layers are deposited and patterned beforehand to define the boundaries and protection zones for subsequent pattern formation steps. This preliminary action prevents defects during the etching of data storage patterns by providing a sacrificial layer that protects underlying structures and ensures precise pattern dimensions, thereby improving reliability while the added complexity is offset by the systematic process sequence.
Data Source
AI summary
A semiconductor device including: first conductive lines on a substrate and extending in a first direction; second conductive lines on the first conductive lines and extending in a second direction; data storage structures between the first and second conductive lines, wherein each of the data storage structures includes a lower data storage electrode, a data storage pattern, and an upper data storage electrode, wherein a width of an upper portion of the lower data storage electrode is smaller than a width of a lower portion of the lower data storage electrode, a width of an upper portion of the data storage pattern is greater than a width of a lower portion of the data storage pattern, and the width of the upper portion of the lower data storage electrode is different from the width of the lower portion of the data storage pattern.