Tapered Die Sidewalls for Dense, Low-Warpage Chip Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable chip packages due to the continuous reduction in feature sizes of semiconductor dies and package components, which affects the integration density and reliability of electronic components.
Innovation Solution
A chip package structure is formed by bonding semiconductor dies over an interposer substrate with a specific insulating layer configuration, where the top die-to-die distance is greater than the bottom die-to-die distance, using a buffer layer to mitigate thermal expansion mismatch and reduce package warpage, and an underfill material layer to support the dies and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes of semiconductor dies and package components are reduced to increase integration density, then more components can be integrated into a given area, but reliability of chip packages deteriorates due to increased warpage and stress
Solution Approach 1:
The patent applies local quality by creating an asymmetric underfill material layer configuration where the first underfill material layer has a different thickness profile than the second underfill material layer. Specifically, the first underfill material layer is thicker at the first end than at the second end, while the second underfill material layer is thicker at the second end than at the first end. This localized variation in material distribution compensates for thermal expansion mismatches and reduces warpage in specific critical areas, thereby maintaining package reliability despite reduced feature sizes and increased integration density.
Solution Approach 2:
The patent employs composite materials by using multiple different underfill material layers (first underfill material layer and second underfill material layer) with different properties and thickness distributions. These composite underfill structures are positioned between adjacent semiconductor dies to provide differential support and stress management. The combination of different materials and their asymmetric arrangement creates a composite system that can simultaneously address thermal expansion mismatches and mechanical stress, improving package reliability while maintaining high integration density.
2Ease of manufacture
If uniform underfill material layer is used between semiconductor dies, then manufacturing process is simplified, but package warpage and tensile stress in redistribution layer increase
Solution Approach 1:
The patent implements local quality by designing underfill material layers with non-uniform thickness distributions tailored to specific locations. The first underfill material layer has increased thickness at the first end, while the second underfill material layer has increased thickness at the second end. This localized thickness variation provides enhanced support where needed, compensating for thermal expansion mismatches and reducing tensile stress in the redistribution layer, thereby controlling package warpage while maintaining manufacturing feasibility through a systematic deposition process.
3Reliability
If larger die-to-die distance is maintained, then stress and warpage are reduced, but structural support and integration density deteriorate
Solution Approach 1:
The patent applies local quality by creating asymmetric underfill material layer configurations that provide localized support at different positions between adjacent semiconductor dies. The first underfill material layer is thicker at the first end, providing support where the first semiconductor die interfaces with the substrate, while the second underfill material layer is thicker at the second end, providing support where the second semiconductor die interfaces. This localized thickness variation allows for reduced overall die-to-die distance while maintaining adequate structural support and stress management, thereby improving integration density without sacrificing reliability.
Solution Approach 2:
The patent employs composite materials by combining multiple underfill material layers with different thickness profiles and material properties. The first underfill material layer and second underfill material layer work together as a composite system, with each layer providing differential support at different locations. This composite underfill structure enables closer spacing of semiconductor dies by distributing mechanical support and thermal stress management across multiple layers with optimized local thickness, thereby maintaining integration density and structural support while reducing overall package warpage and stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability of the chip package by reducing package warpage and tensile-stress in the redistribution layer, increasing the yield and reducing the risk of cold joints and fin-line trace cracks, while maintaining a smaller bottom die-to-die distance for enhanced structural support.
Implementation Method 1
using a buffer layer to mitigate thermal expansion mismatch and reduce package warpage
Implementation Method 2
bonding semiconductor dies over an interposer substrate
Data Source
AI summary
A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.