Tapered Dummy Gate Electrode for Leakage Reduction
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Solution Overview
Problem
The complexity of processing and manufacturing FinFETs increases due to the scaling down of ICs, requiring advanced methods for forming gate stacks that effectively replace dummy gate stacks while minimizing leakage current and parasitic capacitance.
Innovation Solution
A method involving the formation of dummy gate electrode layers, followed by etching processes to create upper and lower portions with distinct sidewall orientations, and subsequent replacement with a tapered lower portion to form a replacement gate stack, which includes dielectric and conductive layers, to enhance the profile and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy gate stacks are replaced with replacement gate stacks in FinFET fabrication, then device performance is improved, but leakage current and parasitic capacitance increase due to proximity between gate stacks and source/drain regions
Solution Approach 1:
The patent applies curvature by forming the lower portion of the dummy gate electrode with a tapered profile instead of a straight vertical sidewall. This curved/tapered geometry increases the distance between the gate stack and source/drain regions, thereby reducing leakage current and parasitic capacitance while maintaining device performance
Solution Approach 2:
The patent applies local quality by creating different sidewall profiles in different portions of the dummy gate electrode. The upper portion maintains a straight sidewall for proper alignment, while the lower portion is tapered to increase spacing from source/drain regions. This localized modification addresses the harmful effects only where needed without compromising overall device structure
2Productivity
If scaling down of ICs is continued to increase functional density, then production efficiency increases and costs decrease, but processing and manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the dummy gate electrode formation into distinct upper and lower portions with different etching processes. The upper portion is etched first to establish alignment, then the lower portion is etched separately with a tapered profile. This segmented approach simplifies the overall manufacturing process by breaking down a complex single-step process into manageable stages
Solution Approach 2:
The patent applies preliminary action by forming the upper portion of the dummy gate electrode first as a preliminary step before forming the lower portion. This preliminary structure serves as a foundation and alignment reference for subsequent processing steps, making the overall fabrication process more controllable and less complex
Data Source
AI summary
A method includes forming a dummy gate electrode layer over a semiconductor region, forming a mask strip over the dummy gate electrode layer, and performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer. A remaining portion of the upper portion of the dummy gate electrode layer forms an upper part of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper part of the dummy gate electrode, and performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, with the protection layer and the mask strip in combination used as a second etching mask. The dummy gate electrode and an underlying dummy gate dielectric are replaced with a replacement gate stack.