Tapered Dummy Gate Spacers to Prevent FinFET Line Collapse
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Solution Overview
Problem
In semiconductor device fabrication, particularly for non-planar transistors like FinFETs and GAA transistors, the challenge lies in preventing line collapse and line twist defects caused by the shrinking size of dummy gates, which affects device yield and performance.
Innovation Solution
The method involves forming tapered dummy gates with a smaller width at the top region and using a sidewall spacer pull-back process to control the dummy gate profile, thereby reducing the risk of line collapse and improving line width roughness and line edge roughness, while also expanding the high-k dielectric metal gate fill process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of dummy gates is reduced to increase device density, then functional density increases, but line collapse and line twist defects occur
Solution Approach 1:
The patent applies asymmetry by forming tapered dummy gates with different widths at the top and bottom. The dummy gate width at the top is smaller than at the bottom, creating an asymmetric structure that reduces line collapse and twist defects while maintaining high device density. This asymmetric geometry provides structural support at the base while minimizing the top width to prevent bridging between adjacent structures.
Solution Approach 2:
The patent changes the geometric parameters of dummy gates by forming them with a tapered profile rather than a uniform width. The width parameter varies along the height of the dummy gate, with the top width being smaller than the bottom width. This parameter change optimizes both device density and structural reliability.
2Quantity of substance
If the size of dummy gates is reduced to increase device density, then functional density increases, but line twist defects occur
Solution Approach 1:
The patent applies asymmetry by forming tapered dummy gates with different widths at the top and bottom. The dummy gate width at the top is smaller than at the bottom, creating an asymmetric structure that reduces line collapse and twist defects while maintaining high device density. This asymmetric geometry provides structural support at the base while minimizing the top width to prevent bridging between adjacent structures.
Solution Approach 2:
The patent changes the geometric parameters of dummy gates by forming them with a tapered profile rather than a uniform width. The width parameter varies along the height of the dummy gate, with the top width being smaller than the bottom width. This parameter change optimizes both device density and structural reliability.
3Ease of manufacture
If conventional dummy gate formation is used, then manufacturing process is simple, but manufacturing precision deteriorates due to line collapse
Solution Approach 1:
The patent applies preliminary action by forming the tapered dummy gates with the correct asymmetric profile before subsequent processing steps. The dummy gates are formed with a tapered profile where the top width is smaller than the bottom width, which prevents line collapse and twist defects in later processing steps. This preliminary structuring ensures manufacturing precision is maintained throughout the fabrication process.
Solution Approach 2:
The patent changes the geometric parameters of dummy gates by forming them with a tapered profile rather than a uniform width. The width parameter varies along the height of the dummy gate, with the top width being smaller than the bottom width. This parameter change optimizes both device density and structural reliability.
Data Source
AI summary
A semiconductor device includes fins above a substrate; a metal gate above the fins; a first dielectric laterally adjacent the metal gate; and sidewall spacers disposed on sidewalls of the metal gate between the metal gate and the first dielectric, the sidewall spacers extending from a bottom region of the first dielectric to a top region of the first dielectric. The sidewall spacers include a first sub-layer and a second sub-layer, the first sub-layer having a first surface contacting the metal gate and an opposite second surface, and the second sub-layer having a third surface contacting the second surface and an opposite fourth surface. An angle between a bottom surface of the second sub-layer, and the third surface, at a point where the bottom surface of the second sub-layer and the third surface intersect each other, is greater than 90 degrees.