Tapered Edge Polysilicon TFT Step Coverage
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Solution Overview
Problem
The existing methods for fabricating polycrystalline silicon thin film transistors face challenges in achieving improved step coverage of the gate insulating layer, leading to reduced breakdown voltage and increased leakage current, which degrades the reliability of the thin film transistor, especially as the thickness of the active layer is reduced.
Innovation Solution
The method involves forming a semiconductor layer with tapered edge portions having a taper angle less than 30 degrees, achieved through a two-stage etching process where the etch rate of the photoresist is greater than that of the silicon layer in the first stage, and the etch rate of the silicon layer is greater than that of the photoresist in the second stage, resulting in a silicon layer with island shapes and improved step coverage for the gate insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional etching process is used to form the active layer, then the fabrication process is simple, but the gate insulating layer has poor step coverage leading to reduced breakdown voltage and increased leakage current
Solution Approach 1:
The etching process is divided into two sequential stages: a first etching process that removes photoresist and forms initial active layer patterns, and a second etching process that refines the active layer edges to create tapered profiles. This segmentation allows each process to be optimized independently, achieving both good step coverage and controlled complexity.
Solution Approach 2:
The first etching process performs preliminary patterning by removing photoresist and forming initial active layer structures. This preliminary action prepares the substrate for the second etching process, which then refines the edges to create the desired tapered profile for improved gate insulating layer coverage.
2Speed
If the active layer thickness is reduced to improve transistor performance, then the switching speed increases, but the step coverage of the gate insulating layer deteriorates further
Solution Approach 1:
The invention changes the geometric parameters of the active layer by creating tapered edge portions with controlled angles. This parameter change allows the gate insulating layer to maintain adequate thickness at the edges even when the overall active layer thickness is reduced, thereby preserving step coverage while enabling faster switching speeds.
3Productivity
If the etch rate of photoresist is greater than that of silicon layer in the first stage, then the photoresist is effectively removed, but the active layer edges become too steep
Solution Approach 1:
The etching process is divided into two sequential stages: a first etching process that removes photoresist and forms initial active layer patterns, and a second etching process that refines the active layer edges to create tapered profiles. This segmentation allows each process to be optimized independently, achieving both good step coverage and controlled complexity.
Solution Approach 2:
The first etching process performs preliminary patterning by removing photoresist and forming initial active layer structures. This preliminary action prepares the substrate for the second etching process, which then refines the edges to create the desired tapered profile for improved gate insulating layer coverage.
4Manufacturing precision
If the etch rate of silicon layer is greater than that of photoresist in the second stage, then the active layer edges are refined, but the photoresist removal is incomplete
Solution Approach 1:
The etching process is divided into two sequential stages: a first etching process that removes photoresist and forms initial active layer patterns, and a second etching process that refines the active layer edges to create tapered profiles. This segmentation allows each process to be optimized independently, achieving both good step coverage and controlled complexity.
Solution Approach 2:
The first etching process performs preliminary patterning by removing photoresist and forming initial active layer structures. This preliminary action prepares the substrate for the second etching process, which then refines the edges to create the desired tapered profile for improved gate insulating layer coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the step coverage of the gate insulating layer, increasing the breakdown voltage and decreasing leakage current, thereby improving the production yield and reliability of the thin film transistor.
Implementation Method 1
performing a first etch process of the photoresist layer and the silicon layer wherein the etch rate of the photoresist in the first etch process is greater than that of the silicon layer; performing a second etch process of the photoresist layer and the silicon layer wherein the etch rate of the semiconductor layer is greater than that of the photoresist
Data Source
AI summary
A thin film transistor includes a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; and a gate electrode disposed on the insulating layer over the channel region, wherein the semiconductor layer includes tapered edge portions with a taper angle defined between the tapered edge portions and a surface of the substrate is less than about 30 degrees.