Tapered Electrode Semiconductor Device Manufacturing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Miniaturization of transistors leads to defects such as disconnection and poor coverage due to the thickness difference between wiring and semiconductor layers, especially when using short-wavelength light sources in photolithography, which complicates the formation of tapered patterns.
Innovation Solution
A semiconductor device manufacturing method involving half etching and reduced resist mask etching to form projecting portions with tapered shapes at the peripheries of electrodes, allowing for improved coverage and reduced defects even with short-wavelength light sources, and utilizing an oxide semiconductor layer for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of the semiconductor layer or gate insulating layer is reduced for miniaturization, then the transistor size is reduced and high-speed operation is achieved, but poor coverage with the wiring occurs causing disconnection or defective connection
Solution Approach 1:
A projecting portion is formed at the periphery of the wiring before forming the semiconductor layer and gate insulating layer. This preliminary structural preparation ensures that when the semiconductor layer and gate insulating layer are formed subsequently, they can properly cover the wiring including the peripheral regions, preventing disconnection and defective connection while enabling miniaturization
2Manufacturing precision
If light with wavelength less than or equal to 365 nm is used for photolithography to improve resolution, then miniaturization is achieved, but it becomes difficult to form tapered shape at the end portion of the pattern degrading coverage
Solution Approach 1:
The wiring structure is segmented into a main body portion and a projecting portion at the periphery. The projecting portion extends in the channel width direction and provides a tapered shape at its end portion. This segmentation allows the use of short-wavelength light for high-resolution patterning while the pre-formed projecting portion ensures proper coverage by the semiconductor layer and gate insulating layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables miniaturization while maintaining favorable characteristics, reducing defects and increasing the number of transistors per substrate, leading to lower manufacturing costs and improved high-speed, low-power operation.
Implementation Method 1
light with a short wavelength less than or equal to 365 nm (i-line) is preferably used as a light source in photolithography in order to improve resolution of the pattern
Data Source
AI summary
An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.