Tapered Columnar Electrodes for Chip Warpage Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The warpage of semiconductor chips makes it difficult to appropriately connect them to wiring substrates, leading to connectivity issues in semiconductor devices.
Innovation Solution
The semiconductor device incorporates columnar electrodes with different tapered shapes extending from conductive connections on the substrate, where one region has a tapered shape that increases in width and another region has a tapered shape that decreases in width, allowing for appropriate connection despite chip warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a semiconductor chip is flipped and connected to a wiring substrate, then the connection is achieved, but warpage of the semiconductor chip makes it difficult to appropriately connect
Solution Approach 1:
The patent applies local quality by creating different pad heights in different regions of the wiring substrate. Specifically, pads in a first region have a first height while pads in a second region have a second height different from the first height. This localized variation in pad height compensates for the warpage of the semiconductor chip, allowing reliable connection despite the chip's non-planar shape.
Solution Approach 2:
The patent introduces a height dimension variation to solve the warpage problem. By forming pads at different heights (first height and second height) rather than a uniform height, the invention adds dimensional diversity to accommodate the chip's warpage, enabling proper electrical connection despite the shape mismatch.
2Ease of manufacture
If uniform pad heights are used on the wiring substrate, then manufacturing is simplified, but connection reliability deteriorates due to chip warpage
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through region-specific pad heights. The wiring substrate is divided into a first region with pads at a first height and a second region with pads at a second height. This approach maintains manufacturing feasibility while significantly improving connection reliability by accommodating chip warpage through localized height variations.
3Reliability
If the wiring substrate is made more complex to accommodate warpage, then connection reliability improves, but device complexity increases
Solution Approach 1:
The patent achieves improved connection reliability with minimal device complexity by using local quality principles. Instead of complexing the entire substrate structure, only specific pads in specific regions are formed at different heights. This localized approach provides the necessary warpage compensation while keeping the overall device structure relatively simple and manufacturable.
Data Source
AI summary
A semiconductor device includes a substrate having a first surface, a second surface opposite to the first surface, conductive connections provided on the first surface, and columnar electrodes each extending from a corresponding one of the conductive connections toward the second surface, each of the columnar electrodes having a tapered shape; and a semiconductor chip having a third surface facing the first surface and a plurality of connection bumps provided on the third surface, each of the plurality of connection bumps electrically connected to a corresponding one of the plurality of conductive connections. A first one of the columnar electrodes, located in a first region of a chip region, has a first tapered shape. A second one of the columnar electrodes, located in a second region of the chip region, has a second tapered shape different from the first tapered shape.