Tapered Fin FET for Enhanced Electrostatic Control
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Solution Overview
Problem
As CMOS devices scale, controlling the channel through conventional means such as doping profile control and gate dielectric scaling becomes increasingly challenging, particularly for fin field effect transistors, trigate transistors, and nanowire transistors, which face short channel behavior due to scaling.
Innovation Solution
A tapered fin field effect transistor is employed, where a stack of a semiconductor fin and a dielectric fin cap with substantially vertical sidewall surfaces is formed on an insulator layer, with the sidewall surfaces passivated by an etch residue material having a tapered thickness profile. An isotropic etch is used to remove the etch residue and expose lower portions of the semiconductor fin, creating a tapered region that allows for greater control of the channel by reducing the lateral width at the bottom portion of the fin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional doping profile control and gate dielectric scaling are used, then device scaling is achieved, but channel control becomes increasingly challenging due to short channel behavior
Solution Approach 1:
The fin structure transitions from a conventional rectangular cross-section to an asymmetric tapered cross-section, where the fin width varies along the vertical direction. The bottom portion of the fin has a narrower width compared to the top portion, creating an asymmetric geometry that improves electrostatic control at the critical channel region while maintaining overall device scaling.
Solution Approach 2:
The tapered fin structure applies local quality by modifying the fin width specifically at the bottom channel region rather than uniformly throughout. This localized geometric modification enhances electrostatic control where it is most needed (at the source-drain interface) without compromising the overall device architecture or upper fin regions.
2Reliability
If the fin width is reduced at the bottom portion, then electrostatic control of the channel is enhanced, but the lateral width reduction may affect current drive capability
Solution Approach 1:
The asymmetric tapered fin geometry concentrates the width reduction at the bottom channel region while maintaining a wider top section. This asymmetric distribution allows the narrow bottom portion to provide superior electrostatic control for threshold voltage modulation, while the wider upper portion preserves sufficient cross-sectional area for carrier transport and current drive capability.
Solution Approach 2:
The invention transitions from controlling device characteristics primarily in the lateral plane to utilizing the vertical dimension for performance optimization. By varying the fin width along the vertical direction (creating a tapered profile), the design exploits the third dimension to simultaneously achieve good electrostatic control at the bottom and adequate current drive through the upper regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The tapered fin structure enhances electrostatic control of the channel, addressing the challenges of scaling in fin field effect transistors by improving control over the channel, thereby mitigating short channel behavior.
Implementation Method 1
The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap
Implementation Method 2
An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin
Implementation Method 3
The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion
Data Source
AI summary
A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.