Tapered Fin Vertical Transistor Sidewall Segmentation

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Solution Overview

Problem

Vertical field-effect transistor (VFET) devices face variability issues in bottom source/drain regions and gate lengths due to fin tapering, which affect device performance and uniformity, leading to challenges in electrostatics and diffusion of dopants.

Innovation Solution

The method involves forming a fin with a tapered profile over a substrate, where a bottom source/drain region is created surrounding the tapered portion, and a bottom spacer is deposited over the source/drain region, reducing the impact of fin tapering on junction and gate formation by isolating the source/drain region with an oxide and using epitaxial growth for uniformity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If fins are formed with standard vertical sidewalls, then manufacturing process is simpler, but fin tapering causes variability in bottom source/drain regions and gate lengths

Engineering Contradiction:

Improvefin taper controlVSAvoidsidewall profile complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fin sidewall is divided into two distinct portions: a first portion with a tapered profile and a second portion with a substantially vertical profile. This segmentation allows each portion to serve different functions - the tapered portion manages stress and doping while the vertical portion ensures precise gate length control, resolving the contradiction between manufacturing precision and device complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the fin sidewall are given different geometric properties - the lower portion has a tapered profile optimized for stress control and doping uniformity, while the upper portion has a vertical profile optimized for gate length precision. This local differentiation resolves the contradiction by allowing each region to be optimized for its specific function

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If fin tapering is reduced to improve gate length control, then manufacturing precision improves, but stress control and doping uniformity in bottom source/drain regions deteriorate

Engineering Contradiction:

Improvegate length controlVSAvoidelectrostatics and doping uniformity

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The sidewall is segmented into tapered and vertical portions, allowing the tapered portion to provide stress control and doping uniformity while the vertical portion ensures gate length control, thus resolving the contradiction between manufacturing precision and reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The lower sidewall region is given a tapered profile to optimize stress and doping characteristics, while the upper sidewall region is given a vertical profile to optimize gate length control, allowing both requirements to be satisfied simultaneously in different locations

Inventive Principle:

Principle #3Local quality

3Reliability

If bottom source/drain regions are formed to surround tapered sidewalls, then doping uniformity improves, but variability in junction formation increases

Engineering Contradiction:

Improvedoping uniformityVSAvoidjunction formation consistency

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

By segmenting the sidewall into tapered and vertical portions, the invention allows the bottom source/drain region to form uniformly around the tapered portion while the vertical portion provides a consistent reference for junction formation, reducing variability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The bottom spacer acts as an intermediary element that is formed around the vertical portion of the sidewall, providing a consistent geometric reference that mediates between the tapered sidewall profile and the required uniform junction formation, thereby reducing variability

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces variability in bottom source/drain and gate regions, improving device performance by minimizing the effect of fin taper profiles on junction and gate formation, leading to more consistent electrostatics and better control over dopant diffusion.

Implementation Method 1

using epitaxial growth for uniformity

Methodology Applied

Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS10985273B2Vertical field-effect transistor including a fin having sidewalls with a tapered bottom profile

Publication Date: 2021.04.20 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.