Tapered Floating Gate Electrode for Nonvolatile Memory Coupling Ratio
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Solution Overview
Problem
In nonvolatile semiconductor memory devices with double-layered gate electrodes, the miniaturization of memory cells leads to reduced capacitance between floating and control gate electrodes, resulting in insufficient coupling ratio and deteriorated cell characteristics, especially when the distance between floating gate electrodes becomes smaller than twice the film thickness of the gate-gate insulating film.
Innovation Solution
The floating gate electrodes are formed with a width in the channel width direction that tapers from a larger lower portion to a smaller upper portion, with the side surface contacting the gate-gate insulating film having a flat or curved surface, allowing the control gate electrode to be fully filled between the floating gate electrodes, thereby maintaining a sufficient coupling ratio and enhancing cell characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the distance between floating gate electrodes is reduced to achieve miniaturization, then the memory cell size is reduced, but the capacitance between floating gate electrode and control gate electrode becomes smaller resulting in insufficient coupling ratio
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a three-dimensional stacked gate structure. The control gate electrode is positioned vertically above the floating gate electrode, creating a layered configuration that increases the effective coupling area without expanding the lateral footprint of the memory cell. This vertical dimensionality change allows sufficient capacitance to be maintained even as the horizontal distance between gates is reduced for miniaturization.
Solution Approach 2:
The control gate electrode is formed to partially fill the space between opposing floating gate electrodes, creating a nested configuration where the control gate is embedded within the vertical space defined by the floating gates. This nesting arrangement maximizes the overlapping area between control and floating gates, thereby maintaining strong capacitive coupling while minimizing the overall cell dimensions.
2Ease of operation
If the control gate electrode is formed of silicon and completely depleted at operation time, then the device operates correctly, but the capacitance between floating gate electrode and control gate electrode becomes smaller resulting in insufficient coupling ratio
Solution Approach 1:
The control gate electrode is constructed as a composite structure with a first control gate electrode layer and a second control gate electrode layer made of different materials. The first layer (closer to the floating gate) is made of a material with higher dielectric constant such as silicide or metal, while the second layer is made of silicon. This composite configuration ensures that the high-capacitance interface is maintained even when the silicon portion is completely depleted during operation, as the silicide or metal layer compensates for the lost capacitance.
3Manufacturing precision
If the floating gate electrodes are formed with convex shape to reduce capacitance between them, then the threshold voltage variation is suppressed, but the step difference makes it difficult to etch the gate-gate insulating film
Solution Approach 1:
Instead of making the entire floating gate electrode convex, the patent applies the convex shape only to specific portions of the floating gate that face each other across the gate-gate insulating film. The side surfaces of the floating gates are formed with substantially flat profiles, creating localized convex regions only where needed to reduce mutual capacitance. This selective application maintains manufacturing simplicity while achieving the desired electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures a stable and efficient coupling ratio of memory cells, preventing deterioration in performance due to miniaturization, while simplifying the etching process of the gate-gate insulating film and allowing for more controlled filling of the control gate electrode, thus improving the overall memory cell characteristics.
Implementation Method 1
the capacitance between the floating gate electrode and the control gate electrode becomes smaller
Implementation Method 2
with a gate-gate insulating film disposed therebetween
Data Source
AI summary
A nonvolatile semiconductor memory device includes a plurality of floating gate electrodes respectively formed above a semiconductor substrate with first insulating films disposed therebetween, and a control gate electrode formed above the plurality of floating gate electrodes with a second insulating film disposed therebetween. In each of the plurality of floating gate electrodes is formed to have a width of an upper portion thereof in a channel width direction which is smaller than a width of a lower portion thereof in the channel width direction and one of contact surfaces thereof on at least opposed sides which contact the second insulating film is formed to have one surface, and the second insulating film has a maximum film thickness in a vertical direction, the maximum film thickness being set smaller than a distance from a lowest surface to a highest surface of the second insulating film in the vertical direction.