Tapered Forksheet Channel Structure for Leakage and Switching Control
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Solution Overview
Problem
Conventional semiconductor IC devices face challenges in maintaining switching speeds and reducing current leakage as device dimensions shrink, particularly in three-dimensional transistors like GAA FETs, where electrostatic control over nanosheets is inadequate.
Innovation Solution
The introduction of a forksheet transistor with tapered channels that have a reduced vertical dimension at the isolation-interface surface, improving electrostatic control by the gate over the channel, which is achieved through selective etching and epitaxial growth of nanolayers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional three-dimensional transistors like GAA FETs are used with uniform nanosheets, then device scaling is achieved, but electrostatic control over the channel is inadequate leading to current leakage and reduced switching speeds
Solution Approach 1:
The patent applies local quality by creating non-uniform nanosheet structures where the channel thickness varies along its length. Specifically, the nanosheets have tapered channels with reduced thickness near the source/drain regions compared to the center region. This local variation in thickness provides enhanced electrostatic control where needed (near sources/drain) while maintaining adequate current flow paths, thereby improving reliability and reducing current leakage without sacrificing device scaling.
2Productivity
If device dimensions are scaled smaller to increase integration density, then productivity is improved, but switching speeds decrease and current leakage increases
Solution Approach 1:
The tapered nanosheet channel structure implements local quality by having different thickness regions: thinner sections near source/drain for improved electrostatic control and faster switching, and thicker center sections for adequate current flow. This local differentiation allows the device to achieve high integration density through scaling while maintaining fast switching speeds and low current leakage through optimized local geometry.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar channels to three-dimensional nanosheet structures with controlled thickness variations. This dimensional change enables enhanced electrostatic control through the vertical dimension while maintaining horizontal scaling for high density. The tapered geometry in the vertical dimension provides superior gate control over the channel compared to uniform planar structures.
3Ease of manufacture
If uniform nanosheet thickness is maintained throughout the channel, then manufacturing is simplified, but electrostatic control near the isolation pillar is insufficient
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through tapered nanosheet channels. The manufacturing process creates non-uniform thickness profiles where the nanosheets are thinner near the isolation pillar and source/drain regions while maintaining greater thickness in the center. This local thickness variation provides enhanced electrostatic control precisely where needed near the isolation pillar, while the overall nanosheet structure remains compatible with existing semiconductor fabrication techniques.
Data Source
AI summary
A forksheet transistor includes a tapered channel that has an interfacial surface that is directly connected to an isolation pillar. The tapered channel has a region in which its cross-sectional vertical dimension reduces in thickness toward its end surface that is in direct contact with the isolation pillar. The tapered channel may improve electrostatic control by the gate of the forksheet transistor over the tapered channel, which may improve the functionality and/or efficiency of the forksheet transistor.