Tapered GAA Gate Structure Profiles to Reduce Parasitic Capacitance
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Solution Overview
Problem
The challenge in forming Gate-All-Around (GAA) FETs is preventing the bottom gate portion from extending into the base structure during the gate replacement process, which increases parasitic capacitance due to the trench formed in the base structure.
Innovation Solution
The solution involves modifying the sacrificial gate structure by forming a portion with a tapered cross-sectional profile on the STI region, which prevents the etching of the STI region and thus avoids the formation of trenches in the base structure, allowing for a substantially planar or narrower bottom surface profile of the bottom gate portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the bottom gate portion extends into the base structure during gate replacement, then the gate structure can be formed, but parasitic capacitance increases due to trench formation in the base structure
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial gate structure with a tapered cross-sectional profile before the actual gate replacement process. This pre-formed structure prevents the bottom gate portion from extending into the base structure during subsequent etching, thereby avoiding trench formation and reducing parasitic capacitance before the problem can occur
Solution Approach 2:
The patent changes the geometric parameter of the sacrificial gate structure by forming it with a tapered cross-sectional profile instead of a rectangular profile. This parameter change in the gate structure geometry controls the etching process to prevent base structure invasion, solving the contradiction between ease of manufacture and parasitic capacitance reduction
2Ease of manufacture
If the sacrificial gate structure has a rectangular cross-sectional profile, then it is easier to form, but it causes trench formation in the base structure increasing parasitic capacitance
Solution Approach 1:
The patent modifies the cross-sectional profile parameter of the sacrificial gate structure from rectangular to tapered. This parameter change alters the etching behavior to prevent horizontal extension into the base structure, thereby eliminating trench formation and the associated parasitic capacitance while maintaining manufacturability
Solution Approach 2:
The patent introduces asymmetry by using a tapered cross-sectional profile for the sacrificial gate structure instead of a symmetric rectangular profile. The asymmetric geometry ensures that the etching process removes material vertically without lateral extension, preventing trench formation in the base structure
Data Source
AI summary
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a base structure with first and second base portions disposed on the substrate, an isolation region disposed on the substrate and adjacent to the base structure, a nanostructured channel region disposed on the first base portion, a source/drain region disposed on the second base portion, a gate structure, and a gate spacer disposed along sidewalls of the gate structure and between the gate structure and the isolation region. The gate structure includes an outer gate portion comprising a tapered cross-sectional profile and disposed on the isolation region and an inner gate portion including a non-tapered cross-sectional profile and disposed on the nanostructured channel region.