Tapered Metal Gate Profile for Sub-3 Nm Channel Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistor dimensions are scaled down to sub-3 nm technology nodes, maintaining gate control and mitigating short-channel effect (SCE) and drain induced barrier lowering (DIBL) in multi-gate semiconductor devices becomes challenging, necessitating further improvements in gate structure design.
Innovation Solution
The method involves forming a gate structure with a tapering gate sidewall profile by employing multiple etching steps with varying strengths during the gate patterning process, resulting in a protruding corner that increases gate critical dimension (CD) closer to the channel region, thereby enhancing gate control and reducing SCE and DIBL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to sub-3 nm technology nodes, then production efficiency increases and costs decrease, but gate control deteriorates and short-channel effect increases
Solution Approach 1:
The patent applies local quality by creating a non-uniform gate structure where the gate width varies along the channel length. Specifically, the gate is wider at the source and drain regions compared to the middle channel region, providing enhanced gate control locally where it is most needed (at the interfaces with source/drain) while maintaining appropriate control in the channel middle. This local variation in gate dimensions directly addresses the gate control deterioration issue at sub-3 nm nodes.
2Productivity
If transistor dimensions are scaled down to sub-3 nm technology nodes, then production efficiency increases and costs decrease, but short-channel effect and drain induced barrier lowering increase
Solution Approach 1:
The non-uniform gate structure with wider regions at source/drain interfaces and a narrower middle region provides enhanced electrostatic control locally where short-channel effects are most pronounced. This local enhancement of gate control suppresses drain induced barrier lowering and short-channel effects without requiring uniform scaling of the entire gate structure.
3Ease of manufacture
If conventional gate structures are used in multi-gate semiconductor devices, then fabrication process is simpler, but gate control is insufficient and short-channel effect cannot be mitigated
Solution Approach 1:
The patent changes the geometric parameters of the gate structure by introducing a non-uniform width profile along the channel length. This parameter change transforms the conventional uniform gate into a tapered or varied-width gate that provides superior gate control and mitigates short-channel effects while remaining compatible with existing fabrication processes.
Data Source
AI summary
A method of forming a semiconductor structure includes depositing a dummy material stack over a fin, patterning a top portion of the dummy material stack in a first etching process, patterning a middle portion of the dummy material stack in a second etching process, patterning a bottom portion of the dummy material stack in a third etching process to form a dummy gate stack, and replacing the dummy gate stack with a metal gate stack. The second etching process is weaker than the first etching process, and the third etching process is weaker than the second etching process.