Tapered Air-Gap Gate Spacers for Gate-to-Contact Capacitance
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Solution Overview
Problem
Semiconductor chips with high transistor densities suffer from parasitic capacitances due to conductive structures being closely spaced, leading to unwanted capacitance issues between transistor gate structures and adjacent source/drain contacts.
Innovation Solution
A method is introduced to form gate spacer structures with air-gaps by creating a gate spacer stack with a sacrificial spacer between two spacer layers, removing the sacrificial spacer to form an opening, etching the opening to create a tapered profile, and sealing it with a low-k dielectric material to reduce the effective dielectric constant and minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conductive structures are placed in close proximity to increase transistor density, then productivity is improved, but parasitic capacitance increases causing harmful electrical effects
Solution Approach 1:
A dielectric layer is introduced as an intermediary substance between conductive structures (gate structures and source/drain contacts) to reduce parasitic capacitance. The dielectric layer with reduced dielectric constant acts as a mediator that maintains electrical isolation while allowing the conductive structures to remain in close proximity for high transistor density.
Solution Approach 2:
The dielectric constant parameter of the insulating material is changed from conventional values to reduced values. By selecting materials with lower dielectric constants, the parasitic capacitance between closely spaced conductive structures is reduced, enabling higher transistor density without the harmful electrical effects of high parasitic capacitance.
2Object-generated harmful factors
If insulating materials with reduced dielectric constant are used to reduce parasitic capacitance, then harmful electrical effects are minimized, but device complexity increases due to additional material selection and process steps
Solution Approach 1:
The dielectric layer serves multiple functions simultaneously: it provides electrical isolation between conductive structures, reduces parasitic capacitance through its low dielectric constant, and maintains structural integrity of the transistor. This multi-functionality reduces the need for additional specialized layers, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The formation of air-gaps within the gate spacer structures effectively reduces parasitic capacitance by lowering the dielectric constant, thereby improving the performance and functionality of densely packed semiconductor chips.
Implementation Method 1
sealing it with a low-k dielectric material to reduce the effective dielectric constant and minimize parasitic capacitance
Data Source
AI summary
The present disclosure describes a method for forming gate spacer structures with air-gaps to reduce the parasitic capacitance between the transistor's gate structures and the source/drain contacts. In some embodiments, the method includes forming a gate structure on a substrate and a spacer stack on sidewall surfaces of the gate structure—where the spacer stack comprises an inner spacer layer in contact with the gate structure, a sacrificial spacer layer on the inner spacer layer, and an outer spacer layer on the sacrificial spacer layer. The method further includes removing the sacrificial spacer layer to form an opening between the inner and outer spacer layers, depositing a polymer material on top surfaces of the inner and outer spacer layers, etching top sidewall surfaces of the inner and outer spacer layers to form a tapered top portion, and depositing a seal material.