Tapered Gate Trench Profile for Reduced Resistance
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Solution Overview
Problem
As transistors shrink in size, the area available for conductive material in the gate trench decreases, leading to increased resistance due to reduced dimensions, especially for metals like tungsten.
Innovation Solution
A modified trench profile with sidewalls of varying widths, where the upper portion has a smaller width than the lower portion, allowing for a self-aligned cap and increased conductive material area without expanding the trench width, using a combination of dielectric layers and liners to enhance conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the transistor size is shrunk to reduce device dimensions, then the device can be miniaturized and more devices can be integrated, but the area available for conductive material in the gate trench decreases, leading to increased resistance
Solution Approach 1:
The patent applies asymmetry by creating a trench with non-uniform width, where the trench is narrower at the top and wider at the bottom. This asymmetric profile allows the conductive material to have a larger cross-sectional area at the bottom where it is needed for current flow, while maintaining a smaller top width to fit within the reduced transistor footprint. The asymmetric trench geometry thus resolves the contradiction between miniaturization and maintaining conductivity.
Solution Approach 2:
The patent utilizes the vertical dimension by varying the trench width through its depth. Instead of maintaining a uniform cross-section, the trench width changes along the vertical axis, creating a three-dimensional conductive path. This dimensional approach allows the conductive material to expand in the vertical direction, increasing its effective area for current flow without increasing the horizontal footprint, thereby maintaining conductivity despite reduced transistor size.
2Area of stationary object
If the trench width is reduced to accommodate smaller transistor dimensions, then device miniaturization is achieved, but the area for conductive material decreases, increasing resistance
Solution Approach 1:
The asymmetric trench profile with different widths at the top and bottom allows the conductive material to have optimized cross-sectional area at each level. The narrower top portion fits within the reduced transistor dimensions, while the wider bottom portion provides sufficient area for low-resistance current flow, thus resolving the contradiction between reduced trench width and maintained conductivity.
Solution Approach 2:
The patent compensates for reduced horizontal trench width by utilizing the vertical dimension. The trench width varies through its depth, creating a three-dimensional conductive path that expands vertically. This allows the conductive material to achieve sufficient cross-sectional area for low resistance without requiring a larger horizontal footprint, thus maintaining conductivity despite reduced trench width.
3Area of moving object
If the gate dimensions are reduced to enable transistor scaling, then device miniaturization is achieved, but the conductive material area decreases, leading to higher resistance
Solution Approach 1:
The asymmetric trench profile enables the conductive material to have different cross-sectional areas at different heights. The material can have a larger area at the bottom where it is needed for current flow, while the top portion is constrained by the reduced gate dimensions. This asymmetric geometry allows the conductive material area to be optimized independently from the overall gate length reduction.
Solution Approach 2:
The patent addresses the reduced conductive material area by utilizing the vertical dimension. The conductive material is configured with varying cross-sectional area through the trench depth, creating a three-dimensional structure that expands vertically to compensate for the reduced horizontal dimensions. This allows the effective conductive area to be maintained despite the reduced gate length and miniaturization.
Data Source
AI summary
The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.