Tapered Insulation Trench for CPODE Pitch Scaling
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Solution Overview
Problem
Existing continuous poly on diffusion edge (CPODE) processes for scaling contacted poly pitch in multi-gate semiconductor devices often damage source/drain epitaxial layers, compromising device performance and reliability.
Innovation Solution
A modified CPODE process involving a single continuous etching step with controlled etch profile forms a tapered trench as insulation between active regions, preventing damage to epitaxial source/drain layers and offering a larger process window for critical dimensions and overlay control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If existing CPODE processes are used to scale contacted poly pitch, then gate pitch reduction is achieved, but source/drain epitaxial layers are damaged
Solution Approach 1:
The patent changes the etching parameters by implementing a tapered etch profile with specific angle constraints (45-85 degrees from horizontal), which modifies how the etch front progresses through the material. This parameter change allows the etch to navigate around the epitaxial layers without damaging them, while still achieving the required gate pitch reduction.
Solution Approach 2:
The patent applies different etching characteristics to different regions: the tapered profile creates a wider opening at the top than at the bottom, allowing the etch to selectively remove material in certain areas while preserving the epitaxial layers in critical regions. This local differentiation of etch quality enables pitch scaling without damage.
2Quantity of substance
If multi-gate devices are scaled to advanced technology nodes, then device density increases, but process complexity increases
Solution Approach 1:
The patent merges the CPODE process with tapered etching into a single integrated process flow. By combining these operations, the patent achieves advanced node scaling without proportionally increasing process complexity, as the tapered profile is implemented within the existing CPODE framework rather than as a separate complex process.
3Reliability
If tapered trench profile is formed with controlled etch, then epitaxial layers are protected, but etch process precision requirements increase
Solution Approach 1:
The patent incorporates feedback mechanisms through the tapered etch profile design, where the etch geometry itself provides guidance on progress and quality. The consistent taper angle (45-85 degrees) serves as a built-in feedback indicator that the etch is proceeding correctly, allowing real-time monitoring and adjustment to maintain epitaxial layer protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified CPODE process enhances device yield by preventing damage to epitaxial source/drain layers, improving reliability and process flexibility, and allowing for more precise control over critical dimensions and pattern overlay.
Implementation Method 1
a single continuous etching step with controlled etch profile forms a tapered trench
Data Source
AI summary
A semiconductor device includes a transistor disposed in an active region. The transistor comprises a source/drain feature, a fin channel and a gate structure wrapping over the fin channel. The transistor also includes an insulation region disposed at an active edge. The active edge is at a boundary of the active region. The insulation region includes a trench. The trench has a tapered portion. A width of the tapered portion of the trench at a top of the fin channel is greater than a width of the tapered portion of the trench at a bottom of the gate structure.