Tapered Inter-Tier Joint in 3D Memory Stacks
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming tapered inter-tier joint regions, which are crucial for enhancing memory density and performance, due to limitations in existing fabrication methods that struggle with precise control over sidewall tapering and material removal rates.
Innovation Solution
The method involves forming a monolithic three-dimensional memory device with a tapered inter-tier joint region by alternately stacking insulating and conductive layers, using a joint dielectric material layer and aspect-ratio-dependent anisotropic etching to create tapered sidewalls, allowing for precise control over the memory film's geometry and integration of a semiconductor channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to form inter-tier joint regions, then manufacturing simplicity is maintained, but manufacturing precision of sidewall tapering deteriorates
Solution Approach 1:
The patent applies parameter changes by utilizing aspect-ratio-dependent anisotropic etching, where the etch rate varies based on the aspect ratio of the cavity being etched. This allows the sidewalls to naturally form with a controlled taper angle without requiring additional patterning steps or complex alignment processes, thereby achieving precise sidewall tapering while maintaining fabrication simplicity.
2Quantity of substance
If memory density is increased through three-dimensional stacking, then storage capacity improves, but manufacturing precision of inter-tier joints deteriorates
Solution Approach 1:
The patent employs self-service through self-aligned processes where the inter-tier memory opening is automatically positioned and sized by the underlying joint level dielectric material layer and alternating stacks. The aspect-ratio-dependent anisotropic etching further enables self-adjustment of the opening dimensions based on the cavity depth, ensuring precise inter-tier joint formation without requiring additional alignment steps, thus maintaining manufacturing precision while enabling high-density three-dimensional stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of memory devices with improved memory density and performance by ensuring precise tapering of sidewalls and efficient integration of memory films, reducing word line leakage and enhancing overall device efficiency.
Implementation Method 1
using a joint dielectric material layer and aspect-ratio-dependent anisotropic etching to create tapered sidewalls
Data Source
AI summary
A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.