Tapered Interconnect Spacing via Vertical Etch
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Solution Overview
Problem
Existing IC interconnect fabrication techniques face challenges in controlling edge-to-edge spacing between adjacent interconnects, particularly when using low-k/ULK dielectric materials, which requires complex and expensive double patterning methods.
Innovation Solution
The method involves forming a cut region in the dielectric layer with a top surface width greater than the bottom surface width, using an etchant that etches the dielectric material more rapidly in the vertical direction, creating a tapered cut region that serves as a template for interconnect sidewalls, allowing for closer spacing between interconnects and increasing interconnect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form cut regions in low-k/ULK dielectric materials, then the dielectric material can be removed, but the edge-to-edge spacing between adjacent interconnects cannot be well-controlled
Solution Approach 1:
A mandrel structure is formed beforehand in the dielectric layer, serving as a template that defines the precise spacing between adjacent interconnects. This preliminary structure guides subsequent etching operations to ensure consistent edge-to-edge spacing. The mandrel is removed after defining the spacing, leaving well-controlled gaps between interconnects.
Solution Approach 2:
The mandrel acts as an intermediary element that temporarily occupies the space between where interconnects will be formed. This intermediary structure enables precise spacing control during fabrication, and is subsequently removed to leave the desired spacing between final interconnect structures.
2Manufacturing precision
If double patterning methods are used to control edge-to-edge spacing, then spacing precision can be improved, but fabrication complexity and cost increase
Solution Approach 1:
The mandrel structure is formed in advance to pre-defin e the spacing pattern, eliminating the need for complex double patterning steps. This preliminary spacing template allows single-step interconnect formation while maintaining precise edge-to-edge spacing control, significantly simplifying the overall fabrication process.
Solution Approach 2:
The mandrel structure serves as a physical copy or template of the desired interconnect spacing pattern. By forming the mandrel first and using it to define the spacing, the complex spacing requirements are transferred to a simpler preliminary structure that can be formed and removed, avoiding complex multi-step patterning.
3Ease of manufacture
If larger spacing is maintained between interconnects, then manufacturing control is easier, but interconnect density decreases
Solution Approach 1:
The mandrel is formed beforehand with dimensions that precisely define the desired minimal spacing between interconnects. This preliminary structure enables fabrication processes to work with tighter spacing than would otherwise be controllable, increasing interconnect density while maintaining manufacturing feasibility through the guiding mandrel structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables well-controlled edge-to-edge spacing between adjacent interconnects, increasing interconnect density without the need for complex patterning stacks, thereby improving the efficiency of IC fabrication.
Implementation Method 1
an etchant that etches the dielectric material more rapidly in the vertical direction, creating a tapered cut region
Data Source
AI summary
Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer. A first interconnect is formed in the first dielectric layer and includes a first top surface, a first bottom surface, and a first sidewall extending from an edge of the first top surface to an edge of the first bottom surface. A second interconnect is formed in the first dielectric layer and includes a second top surface, a second bottom surface, and a second sidewall extending from an edge of the second top surface to an edge of the second bottom surface. A spacing from the edge of the first top surface to the edge of the second top surface is greater than a spacing from the edge of the first bottom surface to the edge of the second bottom surface.