Tapered Interconnection Layer in Semiconductor Packages for Thermal Warpage
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Solution Overview
Problem
The use of materials with different coefficients of thermal expansion in semiconductor packages can lead to issues such as warping or cracking during high-temperature processes, which decreases the connection reliability between the semiconductor chip and the package substrate, posing challenges for achieving reduced weight and high performance in electronic devices.
Innovation Solution
A semiconductor package design that includes a redistribution structure with a lower insulating layer and redistribution layers, a semiconductor chip electrically connected to these layers, an interconnection structure with an upper insulating layer and interconnection layers, and an encapsulant covering the chip and interconnection structure, where the lowermost interconnection layer is designed with a tapered first conductive layer and a surrounding second conductive layer with an outwardly curved surface, enhancing structural integrity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If materials with different coefficients of thermal expansion are used in a package, then weight reduction and high performance are achieved, but warping or cracking occurs during high-temperature processes, decreasing connection reliability
Solution Approach 1:
The lowermost interconnection layer is designed with a tapered shape, where the thickness gradually decreases from the lower surface toward the upper surface. This geometric parameter change allows the interconnection layer to better accommodate thermal expansion differences between materials during high-temperature processes, reducing stress concentration and preventing warping or cracking while maintaining connection reliability
Solution Approach 2:
The interconnection structure employs a composite design with multiple layers including the lowermost interconnection layer with tapered shape, upper interconnection layers, and an encapsulant. This composite structure combines materials with different properties to balance thermal expansion characteristics, providing both mechanical strength and thermal stability to prevent warping and cracking
2Reliability
If a simple interconnection layer design is used, then manufacturing is easier, but structural integrity and reliability under high-temperature conditions are insufficient
Solution Approach 1:
The lowermost interconnection layer features local quality variation through its tapered shape, where the thickness is greater near the lower surface and gradually decreases toward the upper surface. This localized thickness variation provides enhanced structural integrity at the interface with the redistribution structure while reducing overall complexity compared to a uniformly thick multi-layer design
Solution Approach 2:
The lowermost interconnection layer is designed with a curved lower surface that is concave toward the redistribution structure, creating a tapered geometry. This curvature allows for better stress distribution and thermal expansion accommodation, improving structural integrity without requiring complex multi-layer configurations
Data Source
AI summary
A semiconductor package includes a redistribution structure that includes a lower insulating layer, redistribution layers in the lower insulating layer, and first vias connected to the redistribution layers. The semiconductor package further includes a semiconductor chip on an upper surface of the redistribution structure and electrically connected to the redistribution layers; an interconnection structure on the upper surface of the redistribution structure and including an upper insulating layer, a plurality of interconnection layers, and second vias connecting the interconnection layers to each other; an encapsulant covering the semiconductor chip and the interconnection structure; and external connection conductors on a lower surface of the redistribution structure and electrically connected to the redistribution layers. A lowermost interconnection layer includes a first conductive layer contacting a second via and tapered toward the upper surface, and a second conductive layer surrounding the first conductive layer and in contact with a first via.