Tapered Isolation Structure for Cut Metal Gate Reliability
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving reliable electrical isolation between transistors in integrated circuits due to the shrinking size of poly gate structures, leading to reduced yield and increased transistor failures in cutting poly gate schemes.
Innovation Solution
A cut metal gate (CMG) scheme is introduced, utilizing an isolation structure with footing structures that transition from a wider bottom surface to a narrower top surface, formed between adjacent fin structures on a substrate, using insulating materials with high etching selectivity to effectively separate gate metal lines and prevent transistor failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If poly gate structures are shrunk to increase device density, then device density is improved, but electrical isolation between transistors deteriorates leading to reduced yield and increased transistor failures
Solution Approach 1:
The isolation structure is divided into multiple insulating material layers (first insulating material layer, second insulating material layer, third insulating material layer) with different etching selectivities. This segmentation allows each layer to serve a specific function in the etching process, enabling effective gate line separation even as device dimensions shrink, thereby maintaining electrical isolation between transistors while supporting higher device density.
Solution Approach 2:
The multi-layer insulating structure acts as an intermediary between adjacent transistors, providing a controlled interface for gate line separation. The different insulating materials with varying etching selectivities create intermediate zones that facilitate precise isolation during fabrication, preventing direct contact between gate lines of adjacent transistors and maintaining reliability as device density increases.
2Reliability
If cut metal gate scheme is implemented to improve gate line separation, then electrical isolation is improved, but manufacturing complexity increases due to multiple insulating material layers
Solution Approach 1:
The invention utilizes parameter changes in the form of varying etching selectivities among different insulating material layers. By selecting materials with distinctly different etching rates (first layer has highest selectivity, second layer has intermediate selectivity, third layer has lowest selectivity), the process achieves precise gate line separation through selective removal of materials, managing complexity through controlled material property variations rather than structural complexity.
Solution Approach 2:
The isolation structure employs composite materials consisting of multiple insulating material layers with different etching selectivities. This composite approach enables the structure to perform multiple functions: providing electrical isolation, enabling selective gate line removal, and maintaining structural integrity. The composite nature allows the system to achieve reliable gate line separation while managing manufacturing complexity through material property differentiation.
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.