Tapered Liner Contact Structure for Void-Free Semiconductor Integration
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Solution Overview
Problem
The manufacturing and integration of semiconductor devices face challenges such as inadequate step coverage and voids, which can lead to deficiencies in performance and reliability.
Innovation Solution
A semiconductor device structure is designed with a liner layer having a tapered sidewall that improves step coverage and reduces electromigration, along with an inner and outer silicide portion forming a composite landing pad to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing processes are used for semiconductor device integration, then device functionality is achieved, but inadequate step coverage and voids occur leading to performance deficiencies
Solution Approach 1:
The patent changes the geometric parameters of the liner layer by forming it with a tapered sidewall profile instead of a vertical profile. This parameter change allows the liner layer to conformally cover the conductive structure while maintaining adequate thickness, thereby improving step coverage and eliminating voids that lead to performance deficiencies
Solution Approach 2:
The liner layer is designed with an asymmetric tapered profile where the sidewall angle varies from the vertical axis. This asymmetric geometry enables better material deposition and coverage on the conductive structure, resolving the step coverage issue without compromising device reliability
2Reliability
If conventional liner layer structure is used, then device assembly is simplified, but electromigration occurs reducing device reliability
Solution Approach 1:
The patent modifies the liner layer structure by introducing a tapered sidewall with specific angle parameters. This parameter change improves electromigration resistance by ensuring uniform material distribution and reducing stress concentrations, while the tapered geometry itself becomes the defining structural characteristic
3Manufacturing precision
If conventional contact structure is used, then manufacturing process is simple, but high contact resistance and misalignment issues occur
Solution Approach 1:
The contact structure is segmented into multiple functional portions: a liner layer with tapered sidewall, an inner silicide portion, and an outer silicide portion. This segmentation allows each portion to be optimized for its specific function while collectively achieving improved alignment precision and reduced contact resistance
Solution Approach 2:
Different portions of the contact structure are given different local properties: the liner layer provides conformal coverage with tapered geometry, the inner silicide portion provides low contact resistance at the interface, and the outer silicide portion provides structural support. This local quality differentiation resolves both alignment and resistance issues
Data Source
AI summary
A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; a third dielectric layer disposed over the second dielectric layer; a spacer structure disposed in the second dielectric layer; a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer, wherein the conductive structure is surrounded by the spacer structure; a liner layer separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacer structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and an upper plug disposed over the inner silicide portion and the outer silicide portion.