Tapered Liner Sidewall for Void-Free Semiconductor Contacts
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Solution Overview
Problem
The manufacturing and integration of semiconductor devices face challenges such as inadequate step coverage and voids, which can lead to deficiencies in device performance and reliability.
Innovation Solution
A semiconductor device structure is designed with a liner layer having a tapered sidewall, which improves step coverage and reduces electromigration. The structure includes a conductive structure surrounded by a spacer structure and covered by the liner layer, along with inner and outer silicide portions and an upper plug.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional liner layer with vertical sidewall is used, then the manufacturing process is simple, but the step coverage is inadequate and voids occur
Solution Approach 1:
The liner layer is designed with an asymmetric tapered sidewall profile instead of a symmetric vertical sidewall. The sidewall transitions from vertical at the bottom to tapered at the top, creating an asymmetric geometry that improves step coverage and eliminates voids while maintaining manufacturing feasibility through controlled deposition processes.
Solution Approach 2:
The sidewall angle of the liner layer is changed from 90 degrees (vertical) to a tapered angle (e.g., 80-85 degrees at the top), modifying the geometric parameters to achieve better step coverage. This parameter change allows the conformal deposition process to accommodate surface topology variations more effectively.
2Reliability
If the liner layer has vertical sidewall, then the deposition process is straightforward, but voids and inadequate step coverage occur
Solution Approach 1:
The liner layer employs an asymmetric tapered sidewall geometry where the top portion has a different angle than the bottom portion. This asymmetric design ensures complete material coverage on stepped surfaces, eliminating voids that would compromise device reliability, while the complexity is managed through standard deposition techniques.
Solution Approach 2:
Different portions of the liner layer sidewall have different angles optimized for their specific functions: the bottom portion maintains a near-vertical angle for alignment with underlying structures, while the top portion transitions to a tapered angle for improved step coverage and void elimination, ensuring local optimization throughout the structure.
3Reliability
If a simple liner layer structure is used, then manufacturing is easier, but electromigration resistance is insufficient
Solution Approach 1:
The asymmetric tapered sidewall configuration of the liner layer creates a more robust structural profile that better resists electromigration forces. The tapered geometry provides enhanced material distribution and stress management compared to vertical sidewalls, improving electromigration resistance without requiring additional material layers or complex multi-component structures.
Data Source
AI summary
A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; a third dielectric layer disposed over the second dielectric layer; a spacer structure disposed in the second dielectric layer; a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer, wherein the conductive structure is surrounded by the spacer structure; a liner layer separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacer structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and an upper plug disposed over the inner silicide portion and the outer silicide portion.