Tapered Multilayer Memory Cell Array for Consistent Electrical Properties
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Solution Overview
Problem
In nonvolatile semiconductor memory devices with a multilayer structure, the inconsistent properties of memory cells due to varying lamination orders lead to errors in program and read operations.
Innovation Solution
A nonvolatile semiconductor memory device with a memory cell array where memory cells are formed by crossing first and second wires, with variable resistance elements and non-ohmic elements layered in a tapered manner, ensuring consistent ordering and size across layers, and a manufacturing method involving sequential deposition and anisotropic etching to create a multilayer structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are laminated in different orders in the memory cell array, then the memory cell array can have a multilayer structure increasing capacity, but the properties of the memory cells become inconsistent causing errors in program and read operations
Solution Approach 1:
The memory cell array is divided into multiple memory cell layers, with each layer containing memory cells formed by crossing first and second wires. This segmentation allows the array to achieve high capacity through multiple layers while maintaining consistent properties within each layer, resolving the contradiction between capacity increase and operational consistency.
Solution Approach 2:
The patent applies different lamination orders to different regions (layers) of the memory cell array. Specifically, memory cells in different layers are formed with consistent local structures (variable resistance element and non-ohmic element in specific positions), while the overall array achieves high capacity through the multilayer configuration. This local consistency ensures reliable operation despite the complex multilayer structure.
2Manufacturing precision
If memory cells are formed with tapered structure where area gradually becomes smaller from bottom layer towards top layer, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent forms the tapered memory cell structure through preliminary anisotropic etching that creates the tapered shape before subsequent wiring and element formation. This preliminary action establishes the precise tapered geometry early in the manufacturing process, ensuring consistent dimensions across multiple layers while simplifying subsequent fabrication steps despite the increased device complexity.
Data Source
AI summary
A nonvolatile semiconductor memory device includes a memory cell array where a plurality of memory cell layers having a plurality of first and second wires which cross each other and a memory cell provided at each intersection of these first and second wires are laminated on top of each other, wherein the memory cells have a variable resistance element and a non-ohmic element laminated in the direction in which the memory cell layers are laminated and tapered in such a manner that the area in a cross section gradually becomes smaller from the bottom memory cell layer towards the top memory cell layer, and the variable resistance element and the non-ohmic element in the memory cells in a certain memory cell layer are laminated in the same order as the variable resistance element and the non-ohmic element of the memory cells in another memory cell layer.