Tapered Self-Selecting Memory Cell Mitigates Word Line Shorts

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Solution Overview

Problem

Existing memory devices face challenges in increasing memory cell density, reducing manufacturing costs, and improving data retention while minimizing power consumption, particularly in volatile memory architectures like DRAM, which require frequent refreshing and consume significant power.

Innovation Solution

The implementation of self-selecting memory cells with tapered profiles that mitigate shorts between adjacent word lines, enhancing sensing reliability and allowing for more accurate storage of logic states by varying the distribution of ions within the memory cell, thereby improving read/write speeds and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cell density is increased, then storage capacity improves, but manufacturing precision requirements worsen

Engineering Contradiction:
Improvememory cell densityVSAvoidtaper profile precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by modifying the geometric profile of the memory cell from a conventional rectangular shape to a tapered profile. Specifically, the top surface area of the memory cell is reduced relative to the bottom surface area, creating a tapered structure that improves sensing accuracy. This geometric parameter modification enables better differentiation between programmed and unprogrammed states without requiring proportionally higher manufacturing precision across the entire structure.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If sensing accuracy is improved, then data retention improves, but device complexity increases

Engineering Contradiction:
Improvesensing accuracyVSAvoidcell structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements asymmetry by creating an unequal distribution of surface areas within the memory cell structure. The top surface area (where the conductive line contacts) is deliberately made smaller than the bottom surface area, forming an asymmetric tapered profile. This asymmetric geometry concentrates the electric field and ion distribution at specific regions, enhancing sensing accuracy through improved threshold voltage differentiation while maintaining a relatively simple overall cell structure that does not require additional complex components.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach increases memory cell density, reduces manufacturing costs, and enhances data retention by improving sensing accuracy and reducing power consumption, making it suitable for both volatile and non-volatile memory applications.

Implementation Method 1

varying the distribution of ions within the memory cell

Methodology Applied
Scientific EffectIon distribution: Diffusion

Data Source

PatentUS11545625B2Tapered memory cell profiles
Publication Date: 2023.01.03 MICRON TECHNOLOGY INC
  • US11545625B2 patent drawing
  • US11545625B2 patent drawing
  • US11545625B2 patent drawing

AI summary

Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.