Tapered Memory Contacts for Tight-Pitch 3D DRAM Integration
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices, such as DRAM, due to processing conditions and the configuration of control logic devices, which limit the reduction of feature size and performance enhancements like faster speeds and lower power consumption.
Innovation Solution
The design involves a microelectronic device structure with a first microelectronic device attached to a second, where the second structure includes control logic devices vertically overlying memory cells and socket regions for coupling components to BEOL structures, using contact structures with tapered sidewalls to maintain a smaller pitch and compensate for misalignment errors, facilitating tighter digit and word line pitches and larger landing areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If control logic devices are provided in the base control logic structure with conventional routing and contact structures, then the device can be fabricated with standard processing, but the horizontal footprint size and performance (speed, power consumption) are undesirably limited
Solution Approach 1:
The patent transitions control logic devices from a planar arrangement to a three-dimensional configuration where control logic devices are vertically stacked over memory cells. This vertical integration enables tighter pitches and reduces the horizontal footprint while improving performance through shorter interconnect paths and reduced parasitic effects.
Solution Approach 2:
The patent implements nesting by placing control logic devices directly over memory cells in a stacked configuration, with routing structures and contact structures integrated between and around these components. This nested arrangement maximizes space utilization and reduces the overall device footprint.
2Productivity
If feature dimensions are reduced to increase integration density, then the level of integration improves, but processing conditions (temperatures, pressures, materials) limit the achievable configurations and performance
Solution Approach 1:
The patent employs parameter changes by utilizing tapered contact structures with specific aspect ratios and angles, adjusting material compositions and deposition parameters to achieve precise dimensional control at reduced feature sizes. The tapered geometry compensates for processing variations and enables higher integration density within existing manufacturing capabilities.
3Manufacturing precision
If conventional contact structures are used, then fabrication is simpler, but misalignment errors and smaller landing areas limit the achievable pitch and reliability
Solution Approach 1:
The patent applies preliminary action by forming tapered contact structures with enlarged upper surfaces before final alignment and connection steps. This pre-enlarged landing area provides a tolerance buffer that compensates for potential misalignment errors during subsequent processing, thereby improving pitch accuracy and reliability without significantly increasing overall device complexity.
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises memory arrays comprising memory cells comprising access devices and storage node devices, digit lines coupled to the access devices and extending in a first direction to a digit line exit region, and word lines coupled to the access devices and extending in a second direction to a word line exit region. The second microelectronic device structure comprises control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises contact structures individually in contact with the digit lines in the digit line exit region and in electrical communication with at least some of the control logic devices, at least one of the contact structures comprising a first cross-sectional area at an interface of the first microelectronic device structure and the second microelectronic device structure, and a second cross-sectional area at an interface of one of digit lines, the second cross-sectional area smaller than the first cross-sectional area. Related microelectronic devices, memory devices, electronic systems, and methods are also described.