Tapered Memory Pillar Charge Trap Density Uniformity
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Solution Overview
Problem
In NAND-type flash memories, the tapered shape of memory holes leads to variations in electric fields and MONOS film thickness, resulting in uneven write and erase characteristics across memory cells, hindering high-speed operation.
Innovation Solution
The semiconductor memory device features memory cell transistors with tapered semiconductor pillars, varying charge storage layer trap density, and tunnel dielectric film hole passage efficiency, which are designed to address the diameter and electric field disparities by optimizing the structure and manufacturing process of memory holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory holes are formed with conventional processes, then memory cells can be stacked vertically, but the memory holes become tapered causing non-uniform electric fields and varying write/erase characteristics
Solution Approach 1:
The patent applies local quality by varying the trap density of the charge storage layer along the vertical axis of the memory hole. The trap density is increased in the upper portion (bit line side) and decreased in the lower portion (substrate side), creating a non-uniform distribution that compensates for the tapered hole shape and achieves uniform electric fields throughout the memory cell stack.
2Quantity of substance
If the number of stacked layers is increased to enhance capacity, then memory device density improves, but the aspect ratio of memory holes increases causing greater diameter variation and electric field non-uniformity
Solution Approach 1:
The patent employs parameter changes by adjusting the trap density parameter of the charge storage layer as a function of position. Specifically, the trap density is modified to increase toward the upper portion of the memory hole, which compensates for the increased aspect ratio effects and maintains uniform electric fields even when the number of stacked layers is increased.
3Ease of manufacture
If conventional MONOS film formation is used, then memory cells can be formed in tapered holes, but the MONOS film thickness varies leading to inconsistent write and erase speeds
Solution Approach 1:
The patent applies local quality by creating a charge storage layer with spatially varying trap density. The trap density is engineered to be higher in the upper portion and lower in the lower portion, which compensates for the tapered hole geometry and achieves uniform electric fields and consistent write/erase characteristics across all memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the uniformity of write and erase speeds across memory cells, enabling high-speed operation by adjusting trap density and hole passage efficiency to match the tapered hole shape, thereby reducing variations and enhancing device performance.
Implementation Method 1
a tunnel dielectric film which increases in hole passage efficiency from the first select transistor toward the second select transistor
Data Source
AI summary
A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.