Tapered Metal Gate Transistor via Stressed ILD Shrinkage
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in adequately filling trenches with metal gate electrodes during the replacement gate process, particularly due to varying trench profiles caused by localized etching effects, which can result in voids and affect electrical properties and yield, especially as feature sizes decrease.
Innovation Solution
A method involving the use of a dummy gate stack with a vertical profile to self-align implantation processes, followed by stressing a tensile inter-level dielectric (ILD) layer to increase cross-linking and shrinkage, creating a tapered trench profile that is easier to fill without voids, and performing stress treatment before or after dummy gate removal to ensure effective trench filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a vertical dummy gate profile is used for self-aligned implantation, then implantation alignment is improved, but trench filling becomes difficult due to re-entrant profiles
Solution Approach 1:
The patent applies preliminary action by forming a tensile ILD layer before dummy gate removal. This tensile layer is subsequently relaxed to induce compressive stress that shrinks the ILD and pulls spacers away from the trench, creating a tapered profile that facilitates filling. The preliminary formation of the tensile ILD layer with specific properties enables the subsequent profile transformation without requiring process changes to the implantation alignment.
Solution Approach 2:
The patent changes the physical and chemical parameters of the ILD layer by forming it with tensile stress initially, then relaxing this stress to induce compressive conditions. This parameter transformation causes the ILD to shrink and the trench profile to evolve from re-entrant to tapered, solving the filling difficulty while maintaining the vertical dummy gate for alignment.
2Ease of manufacture
If the ILD layer is made tensile to facilitate trench filling, then filling ease is improved, but ILD structural integrity may be compromised
Solution Approach 1:
The patent applies dynamics by transforming the ILD layer from a static structure to a dynamic one that changes its mechanical properties through stress relaxation. The ILD layer transitions from a tensile state during deposition to a compressive state after relaxation, enabling it to actively pull spacers away and create the desired tapered profile while maintaining structural integrity throughout the process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures complete trench filling with a wider top and easier etching, reducing voids and maintaining structural integrity, thereby improving yield and electrical properties of transistors by creating a trapezoidal metal gate profile with a wider top and bottom.
Implementation Method 1
stressing a tensile inter-level dielectric (ILD) layer to increase cross-linking and shrinkage
Implementation Method 2
stressing a tensile inter-level dielectric (ILD) layer to increase cross-linking and shrinkage
Data Source
AI summary
A semiconductor device having arrays of metal gate transistors is fabricated by forming a number of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer, depositing a tensile ILD layer between the dummy gate structures, stressing the tensile ILD layer, removing at least the dummy gate material to form a number of trenches, and depositing a metal gate material in the trenches, which have a tapered profile.