Tapered P-Type Columns in Vertical Power MOSFETs
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Solution Overview
Problem
In vertical power MOSFETs with superjunction structures, increasing the aspect ratio of p-type column regions to reduce on resistance while maintaining withstand voltage is challenging due to variations in p-type column region impurity concentration, leading to reliability issues and yield reductions.
Innovation Solution
The formation of p-type semiconductor regions with tapered sides adjacent to p-type column regions, allowing for a larger charge balance margin and improved impurity concentration tolerance, is achieved through diagonal ion implantation and epitaxial growth, enabling increased aspect ratios without compromising withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the aspect ratio of p-type column regions is increased to reduce on resistance, then on resistance decreases, but impurity concentration varies leading to reduced reliability
Solution Approach 1:
The patent applies preliminary action by forming a tapered structure in the groove before filling it with p-type epitaxial layer. The groove has a wider opening at the top and narrows toward the bottom, which pre-compensates for the variation in impurity concentration that would occur during epitaxial growth. This preliminary geometric configuration ensures that even as the aspect ratio increases, the impurity concentration remains more uniform throughout the p-type column region, thereby maintaining both low on-resistance and high reliability.
2Reliability
If the aspect ratio of p-type column regions is increased, then on resistance decreases, but withstand voltage cannot be maintained
Solution Approach 1:
The patent applies asymmetry by creating a groove with non-uniform cross-section along its depth. The groove width varies from top to bottom, forming a tapered shape rather than a uniform cylindrical structure. This asymmetric geometry allows the p-type column to achieve a higher aspect ratio while maintaining controlled impurity concentration distribution, enabling both low on-resistance and maintained withstand voltage capability.
3Productivity
If p-type column regions with high aspect ratio are formed, then on resistance is reduced, but device yield decreases
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of the groove structure. Specifically, the groove is designed with a tapered profile where the width changes continuously from the top opening to the bottom. This parameter variation along the groove depth allows the p-type column to achieve high aspect ratio for reduced on-resistance while the changing cross-sectional area compensates for impurity concentration variations, thereby maintaining device yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and yield of vertical power MOSFETs by maintaining high withstand voltage and reducing on resistance, improving overall semiconductor device performance.
Implementation Method 1
a device isolation region embedded in a groove around a fin includes a silicon oxide film and a silicon nitride film that are sequentially stacked from the bottom of the groove
Implementation Method 2
a device isolation region embedded in a groove around a fin includes a silicon oxide film and a silicon nitride film that are sequentially stacked from the bottom of the groove
Implementation Method 3
The formation of p-type semiconductor regions with tapered sides adjacent to p-type column regions, allowing for a larger charge balance margin and improved impurity concentration tolerance, is achieved through diagonal ion implantation and epitaxial growth
Implementation Method 4
The formation of p-type semiconductor regions with tapered sides adjacent to p-type column regions, allowing for a larger charge balance margin and improved impurity concentration tolerance, is achieved through diagonal ion implantation and epitaxial growth
Data Source
AI summary
In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.