Back-to-Back Tapered Sections for Photonics Chip Stitching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Positional mismatches during reticle stitching in photonics chip fabrication lead to misalignment of waveguide cores at boundaries, resulting in performance degradation such as elevated insertion loss and increased back reflection.

Innovation Solution

The implementation of tapered waveguide cores with increasing width dimensions across boundaries, allowing for efficient light transmission and improved tolerance to misalignment due to back-to-back tapered sections that align and transfer light across the boundary.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If reticle stitching is used to pattern large photonics chips, then manufacturing area and productivity are improved, but manufacturing precision deteriorates due to positional mismatches at boundaries

Engineering Contradiction:
Improvemanufacturing areaVSAvoidwaveguide core alignment
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The waveguide core width parameter is changed dynamically across the boundary region. The tapered sections create a gradual width transition from the first waveguide core to the second waveguide core, allowing the structure to adapt to positional mismatches while maintaining optical performance. This parameter change enables the system to tolerate manufacturing variations introduced during reticle stitching.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If waveguide cores are aligned precisely across reticle boundaries, then performance is improved, but device complexity increases due to additional alignment mechanisms

Engineering Contradiction:
Improvelight transmission efficiencyVSAvoidalignment structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The tapered waveguide core structure is applied locally only at the boundary regions where reticle stitching occurs, rather than throughout the entire chip. This localized approach addresses the specific problem of misalignment at boundaries while maintaining simple, standard waveguide structures in the bulk areas, thereby avoiding unnecessary complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The tapered sections act as an intermediary structure between the first and second waveguide cores. These tapered regions serve as a transition zone that mediates the optical coupling between misaligned waveguide cores, enabling efficient light transmission without requiring complex active alignment mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the impact of reticle stitching mismatches, enhances light transfer across boundaries, and increases tolerance to misalignment, thereby improving the performance and reliability of photonics chips.

Implementation Method 1

The first tapered section has a first width dimension that increases with increasing distance from the boundary, and the second tapered section has a second width dimension that increases with increasing distance from the boundary

Methodology Applied
Scientific EffectOptical mode transfer: Waveguide (optics)

Data Source

PatentUS11880066B2Photonics chips with reticle stitching by back-to-back tapered sections
Publication Date: 2024.01.23 GLOBALFOUNDRIES US INC
  • US11880066B2 patent drawing
  • US11880066B2 patent drawing
  • US11880066B2 patent drawing

AI summary

Structures including a waveguide core and methods of fabricating a structure including a waveguide core. The structure comprises a photonics chip including a first chip region, a second chip region, a first waveguide core in the first chip region, and a second waveguide core in the second chip region. The first chip region adjoins the second chip region along a boundary. The first waveguide core includes a first tapered section, and the second waveguide core includes a second tapered section positioned across the boundary from the first tapered section. The first tapered section has a first width dimension that increases with increasing distance from the boundary, and the second tapered section has a second width dimension that increases with increasing distance from the boundary.