Tapered Plug Structure for DRAM Contact Resistance
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Solution Overview
Problem
In semiconductor devices, the reduced space between plugs leads to increased contact resistance due to tapered via-plugs, which complicates the control of plug diameter during wet etching, potentially causing short-circuit failures.
Innovation Solution
A semiconductor device structure with a first plug and a second plug, where the second plug has a diameter increasing from a smaller top portion to a larger bottom portion, formed using a combination of anisotropic and isotropic etching processes to enhance contact area without causing short-circuits, involving a top insulating film with a conical shape and interlayer dielectric films with varying impurity concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the diameter of via-holes is increased to reduce contact resistance, then the contact area between plugs is improved, but the risk of short-circuit failure between adjacent interconnections increases
Solution Approach 1:
The via-plug is designed with non-uniform diameter along its length, creating local quality variations. The lower portion has a larger diameter to reduce contact resistance, while the upper portion maintains a smaller diameter to prevent short-circuit failures. This localized differentiation resolves the contradiction by optimizing each section for its specific functional requirement.
Solution Approach 2:
The via-plug is segmented into two distinct portions: a first portion with smaller diameter and a second portion with larger diameter. This segmentation allows independent optimization of each segment - the upper segment prevents short-circuits while the lower segment ensures low contact resistance, thereby resolving the technical contradiction.
2Productivity
If the diameter of plugs is reduced to prevent short-circuit failures, then the integration density is improved, but the contact area between plugs is reduced, increasing contact resistance
Solution Approach 1:
The via-plug structure implements local quality by having different diameters at different heights. The upper portion maintains small diameter for high integration density, while the lower portion expands to provide sufficient contact area, thus resolving the contradiction between integration density and contact resistance.
Solution Approach 2:
The plug is divided into segments with different diameters - the upper segment is narrow for density while the lower segment is wider for contact area. This segmentation enables both high integration density and low contact resistance to coexist, resolving the technical contradiction.
3Reliability
If wet etching is used to enlarge the diameter of via-holes, then the contact area is improved, but the control of plug diameter becomes difficult, potentially causing short-circuits
Solution Approach 1:
The invention changes the parameter of etch selectivity by using a two-layer interlayer dielectric structure with different impurity concentrations. The lower layer has higher phosphorus concentration and thus higher etch rate, allowing controlled enlargement of via-hole diameter at the lower portion while maintaining precision through the selective etching process.
Solution Approach 2:
The lower interlayer dielectric layer acts as an intermediary that enables controlled diameter enlargement. By having different etch selectivity compared to the upper layer, it mediates the etching process to achieve the desired tapered shape with precise diameter control, preventing short-circuits while enlarging contact area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively enlarges the contact area between plugs while preventing short-circuit failures by carefully controlling the plug diameter, ensuring reliable interconnection in high-density DRAM devices.
Implementation Method 1
the lower interlayer dielectric layer is selectively etched by a wet etching process to enlarge the diameter in the vicinity of the bottom of the via-holes
Implementation Method 2
the etch rate of the lower interlayer dielectric layer is higher than that of the upper interlayer dielectric layer
Data Source
AI summary
A semiconductor device includes: first and second interlayer dielectric films consecutively deposited to overlie a silicon substrate; contact plugs penetrating the first interlayer dielectric film and having a top surface located within the second interlayer dielectric film; and via-plugs having a first portion, the diameter of which reduces from the top of the second interlevel dielectric film toward the bottom thereof and a second portion extending between the first portion and the first plug, the second portion having a diameter increasing from the first portion to the first plug.