Tapered Profile Substrate for 3DIC Via Isolation
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Solution Overview
Problem
In three-dimensional integrated circuit (3DIC) packaging, existing through via technologies face challenges in reducing the size of integrated circuits and preventing electrical leakage paths, known as seams, which affect the isolation between the redistribution layer and the substrate.
Innovation Solution
The implementation of a tapered profile portion in the substrate surrounding the through via, combined with a dielectric capping layer and a redistribution layer, effectively isolates the electrical components by reducing the formation of seams and enhancing the geometry for better capping, using materials like silicon and copper, and employing chemical mechanical polishing for substrate planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If through via technology is used to reduce the size of integrated circuits, then the footprint is reduced and electrical paths are shortened, but electrical leakage paths (seams) may form between the redistribution layer and substrate
Solution Approach 1:
The substrate is divided into a first portion and a second portion, creating a segmented structure that prevents continuous electrical leakage paths. The first portion with tapered surface and the second portion with planar surface create discontinuities that block seam formation while maintaining compact footprint.
Solution Approach 2:
Different portions of the substrate are given different surface characteristics - the first portion has a tapered surface while the second portion has a planar surface. This local differentiation in surface quality prevents seams at critical interfaces while maintaining overall electrical isolation.
2Reliability
If a tapered profile portion is added to the substrate to prevent seams, then electrical isolation is improved, but the device complexity increases
Solution Approach 1:
The substrate structure is extended into the vertical dimension with a tapered profile portion, transforming a potentially complex lateral structure into a more manageable vertical geometry. This dimensional approach simplifies the overall device complexity while maintaining effective electrical isolation.
3Manufacturing precision
If the substrate is planarized using chemical mechanical polishing, then the surface finish is improved for better capping, but the manufacturing process complexity increases
Solution Approach 1:
The substrate is planarized using chemical mechanical polishing before the capping layer is deposited. This preliminary surface preparation ensures optimal surface finish for subsequent capping operations, preventing defects and improving manufacturing yield despite the additional process step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces electrical leakage paths, maintains electrical isolation, and allows for a more compact and efficient 3DIC structure with faster operation by preventing seams and optimizing the capping of the dielectric layer.
Implementation Method 1
employing chemical mechanical polishing for substrate planarization
Data Source
AI summary
An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.