Tapered Semiconductor Line Patterns for RC Delay Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently transmitting signals from pad patterns to line patterns due to high resistance, leading to increased RC delay and reduced operating speed of memory cells.
Innovation Solution
The semiconductor device incorporates conductive patterns with pad patterns extending in one direction and line patterns crossing perpendicularly, where the line patterns have a tapered shape with increasing width towards the pad pattern, reducing resistance and enhancing signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If line patterns have uniform width, then manufacturing is simple, but resistance is high causing increased RC delay
Solution Approach 1:
The line pattern width is varied locally: wider at the pad pattern end to reduce resistance, and narrower at the memory cell end. This local quality change optimizes signal transmission by reducing RC delay at the high-resistance pad interface while maintaining acceptable layout density elsewhere.
Solution Approach 2:
The geometric parameter of line pattern width is changed along its length, transitioning from a uniform width design to a tapered width design. This parameter variation allows the line pattern to achieve lower resistance near the pad pattern, directly addressing the RC delay issue.
2Reliability
If line patterns have wider width at pad pattern end, then resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The line pattern width parameter is systematically varied along its length, creating a controlled gradient from wider to narrower sections. This gradual parameter change reduces abrupt transitions that would be difficult to manufacture, while still achieving the resistance reduction benefit.
Data Source
AI summary
A semiconductor device may include first conductive patterns and first interlayer insulating layers. Each of the first conductive patterns may include a first pad pattern extending in a first direction and first line patterns extending from the first pad pattern in a second direction crossing the first direction, widths of the first line patterns increasing as a distance from the first pad pattern decreases. The first conductive patterns and the first interlayer insulating layers may be stacked on top of each other.