Tapered Semiconductor Pillars for Uniform Memory Cell Currents
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Solution Overview
Problem
The existing cross-point processing method for stacked memory devices results in varying gate areas and threshold voltages due to uneven shallow trench isolation films, leading to inconsistent write and erase voltages, and reduced cell currents at the bottom portions of semiconductor pillars.
Innovation Solution
The semiconductor storage device employs a configuration where charge accumulation layers are formed on both sides of semiconductor pillars with a tapered shape, having a larger width at the bottom ends than at the top ends, and using sacrifice films to maintain consistent cross-sectional areas and reduce processing conversion differences, thereby stabilizing threshold voltages and cell currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If shallow trench isolation films are used in cross-point processing, then memory holes can be formed at cross-points, but the memory holes become wide at top ends and narrow at bottom ends due to etching depositions, causing variation in gate area and threshold voltage
Solution Approach 1:
The patent changes the material parameter of the isolation film from conventional silicon dioxide to a material with lower etching deposition (such as silicon nitride or carbon-based materials). This parameter change reduces the etching conversion difference, allowing memory holes to maintain more uniform cross-sectional areas from top to bottom, thereby improving gate area consistency and reducing threshold voltage variation
Solution Approach 2:
The patent uses sacrifice films (such as silicon oxide or silicon nitride) that are deposited conformally and then removed to define the memory hole pattern. This copying approach allows the memory hole shape to be defined by the sacrifice film pattern rather than by direct etching of the isolation film, eliminating the taper effect caused by etching depositions
2Reliability
If shallow trench isolation films are processed, then memory holes are formed, but cell currents in memory cells at the bottom portions of the semiconductor pillars are adversely reduced due to large cross-sectional area variation
Solution Approach 1:
The patent changes the etching characteristics by using alternative isolation film materials or etching conditions that reduce deposition, thereby maintaining more uniform semiconductor pillar cross-sectional areas. This ensures consistent cell currents across all memory cells in the stack, improving reliability
Solution Approach 2:
The patent aims to create equipotential conditions for current flow by ensuring uniform cross-sectional areas throughout the semiconductor pillars. By eliminating the taper effect, the electrical path resistance becomes consistent across all memory cells, ensuring uniform cell currents and reliable memory operation
3Productivity
If cross-point processing is used to improve integration degree, then charge accumulation layers and control electrodes can be formed on side surfaces, but threshold voltages and write/erase voltages vary according to memory cell position
Solution Approach 1:
The patent changes the isolation film material parameter to reduce etching deposition, which maintains uniform memory hole dimensions throughout the stack. This eliminates the position-dependent variation in gate area, thereby ensuring consistent threshold voltages and write/erase voltages across all memory cells while maintaining high integration density through the cross-point architecture
Data Source
AI summary
A semiconductor storage device according to an embodiment comprises stacks comprising insulating films and first wires that are alternately stacked. Semiconductor parts are provided in the stacks. The longitudinal direction of the semiconductor parts is a stacking direction of the insulating films and the first wires. Charge accumulation layers are provided between the first wires and the semiconductor parts and a plurality of the charge accumulation layers are provided corresponding to one of the semiconductor parts in a cross-section in a direction perpendicular to the longitudinal direction of the semiconductor parts. A width of first side surfaces of the semiconductor parts on which the charge accumulation layers are provided is larger at bottom ends of the semiconductor parts than at top ends of the semiconductor parts.