Tapered Silicon Pillar Memory Device Voltage Optimization
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Solution Overview
Problem
The reliability of nonvolatile semiconductor memory devices with a BiCS structure is compromised due to varying cross-sectional areas of silicon pillars, leading to over-deletion states during memory cell deletion operations, as the etching perpendicularity degrades and threshold voltages fluctuate across different layers.
Innovation Solution
The nonvolatile semiconductor memory device employs a tapered silicon pillar design with varying cross-sectional areas, where voltages applied to word lines are optimized based on the pillar dimensions to prevent over-deletion by matching the voltage to the threshold voltage of each memory transistor, ensuring reliable data deletion across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a laminate structure with alternating conductive word line layers and inter-word line insulating films is used to increase capacity and reduce cost, then the number of layers increases and cost per bit decreases, but the perpendicularity of etching degrades causing varying hole cross-sectional areas at different depths
Solution Approach 1:
The patent applies local quality by making the word line conductive films have different potentials according to their depth in the laminate structure. Memory cells at different depths are subjected to different voltages during deletion operations, with deeper cells receiving higher voltages to compensate for their smaller cross-sectional areas. This localized differentiation resolves the etching perpendicularity issue by adapting the electrical characteristics to the physical variations caused by the etching process.
2Ease of operation
If deletion is performed for a block of memory cells on various layers at a constant voltage, then the operation is simple, but an over-deletion state occurs in some memory cells leading to reliability degradation
Solution Approach 1:
The patent changes the voltage parameter applied to word line conductive films based on their depth position in the laminate structure. During deletion operations, different voltages are applied to different layers, with higher voltages applied to deeper layers that have smaller cross-sectional areas. This parameter differentiation prevents over-deletion in deeper cells while maintaining simple block-level deletion operations, thus resolving the contradiction between operational simplicity and reliability.
Data Source
AI summary
A nonvolatile semiconductor memory device includes a semiconductor substrate and memory transistors, each of which has a laminate formed by alternately laminating insulating films and conductive films on the semiconductor substrate, a silicon pillar going through the laminate, a tunnel insulating film arranged on the surface of the silicon pillar facing the laminate, a charge accumulating layer arranged on the surface of the tunnel insulating film facing the laminate, and a block insulating film arranged on the surface of the charge accumulating layer facing the laminate and in contact with the conductive film. During a data deletion operation, a voltage is applied on the conductive film so that the potential of the silicon pillar with respect to the conductive film decreases as the cross-sectional area of the silicon pillar decreases.